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| Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd w 528-channel 6-bit Source Driver with System-on-chip for Color Amorphous TFT-LCDs w w .m bt re SPFD54126B nd .co Preliminary NOV. 20, 2006 Version 0.2 Contact ORISE Technology to ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document. obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent or other rights of third parties which may result from its use. In addition, ORISE products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of ORISE. m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table of Contents PAGE TABLE OF CONTENTS .......................................................................................................................................................................................... 2 1. GENERAL DESCRIPTION .......................................................................................................................................................................... 6 2. FEATURE .................................................................................................................................................................................................... 6 3. ORDERING INFORMATION........................................................................................................................................................................ 6 4. BLOCK DIAGRAM ...................................................................................................................................................................................... 7 4.1. BLOCK FUNCTION .................................................................................................................................................................................. 7 4.1.1. System Interface ....................................................................................................................................................................... 8 4.1.2. External Display Interface ......................................................................................................................................................... 8 4.1.5. Grayscale Voltage Generating Circuit....................................................................................................................................... 8 4.1.6. Timing Controller....................................................................................................................................................................... 8 4.1.7. Oscillator (OSC) ........................................................................................................................................................................ 8 4.1.8. Source Driver Circuit................................................................................................................................................................. 8 4.1.9. Gate Driver Circuit .................................................................................................................................................................... 9 6. INSTRUCTIONS ........................................................................................................................................................................................ 15 6.1.1. System Function Command List and Description ................................................................................................................... 15 6.1.2. Panel Function Command List and Description...................................................................................................................... 18 6.2.1. NOP (00h) ............................................................................................................................................................................... 23 6.2.2. SWRESET (01h): Software Reset .......................................................................................................................................... 24 6.2.3. RDDID (04H): Read Display ID............................................................................................................................................... 25 6.2.4. RDDST (09H): Read Display Status ....................................................................................................................................... 26 6.2.5. RDDPM (0AH): Read Display Power Mode............................................................................................................................ 28 6.2.6. RDDMADCTR (0BH): Read Display MADCTR....................................................................................................................... 29 6.2.7. RDDCOLMOD (0CH): Read Display Pixel Format ................................................................................................................. 30 6.2.8. RDDIM (0DH): Read Display Image Mode ............................................................................................................................. 31 6.2.9. RDDSM (0EH): Read Display Signal Mode ............................................................................................................................ 32 6.2.10. 6.2.11. 6.2.12. 6.2.13. 6.2.14. 6.2.15. 6.2.16. 6.2.17. 6.2.18. 6.2.19. 6.2.20. RDDSDR (0FH): Read Display Self-Diagnostic Result ...................................................................................................... 33 SLPIN (10H): Sleep In ........................................................................................................................................................ 34 SLPOUT (11H): Sleep Out ................................................................................................................................................. 36 PTLON (12H): Partial Display Mode On............................................................................................................................. 38 NORON (13H): Normal Display Mode On .......................................................................................................................... 39 INVOFF (20H): Display Inversion Off ................................................................................................................................. 40 INVON (21H): Display Inversion On ................................................................................................................................... 41 GAMSET (26H): Gamma Set ............................................................................................................................................. 42 DISPOFF (28H): Display Off .............................................................................................................................................. 43 DISPON (29H): Display On ................................................................................................................................................ 45 CASET (2AH): Column Address Set .................................................................................................................................. 47 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w 6.2. SYSTEM COMMAND DESCRIPTION ........................................................................................................................................................ 23 w w 6.1. OUTLINE.............................................................................................................................................................................................. 15 .m 5. SIGNAL DESCRIPTIONS.......................................................................................................................................................................... 10 bt 2 4.1.10. LCD Driving Power Supply Circuit........................................................................................................................................ 9 re nd .co 4.1.4. Graphics RAM (GRAM) ............................................................................................................................................................ 8 m 4.1.3. Address Counter (AC)............................................................................................................................................................... 8 NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.21. 6.2.22. 6.2.23. 6.2.24. 6.2.25. 6.2.26. 6.2.27. 6.2.28. 6.2.29. 6.2.30. 6.2.31. 6.2.32. 6.2.33. 6.2.34. 6.2.35. 6.2.36. 6.2.37. 6.2.38. 6.2.39. 6.2.40. 6.2.41. RASET (2BH): Row Address Set........................................................................................................................................ 49 RAMWR (2CH): Memory Write........................................................................................................................................... 51 RGBSET (2DH): Colour Setting ......................................................................................................................................... 53 RAMHD (2EH): Memory Read ........................................................................................................................................... 54 PTLAR (30H): Partial Area ................................................................................................................................................. 55 SCRLAR (33H): Scroll Area................................................................................................................................................ 58 TEOFF (34H): Tearing Effect Line OFF.............................................................................................................................. 62 TEON (35H): Tearing Effect Line ON ................................................................................................................................. 63 MADCTR (36H): Memory Data Access Control.................................................................................................................. 64 VSCSAD (37H): Vertical Scroll Start Address of RAM ....................................................................................................... 66 IDMOFF (38H): Idle Mode Off ............................................................................................................................................ 68 IDMON (39H): Idle Mode On .............................................................................................................................................. 69 RDID1 (DAH): Read ID1 Value........................................................................................................................................... 72 RDID2 (DBH): Read ID2 Value........................................................................................................................................... 73 RDID3 (DCH): Read ID3 Value .......................................................................................................................................... 74 SRGBOFF (ABH): Separate RGB Gamma ON.................................................................................................................. 76 VSYNCOFF (ACH): VSYNC Interface OFF ....................................................................................................................... 77 VSCTR1 (AEH): VSYNC Interface function control 1......................................................................................................... 79 6.3.1. RGBCTR (B0H): RGB signal control ...................................................................................................................................... 80 6.3.2. FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)..................................................................................... 81 6.3.4. FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)....................................................................................... 85 6.3.5. INVCTR (B4h): Display Inversion Control............................................................................................................................... 87 6.3.6. RGBBPCTR (B5h): RGB Interface Blanking Porch setting..................................................................................................... 88 6.3.7. DISSET5 (B6h): Display Function set 5.................................................................................................................................. 89 6.3.8. PWCTR1 (C0H): Power Control 1 .......................................................................................................................................... 91 6.3.9. PWCTR2 (C1H): Power Control 2 .......................................................................................................................................... 93 6.3.10. 6.3.11. 6.3.12. 6.3.13. 6.3.14. 6.3.15. 6.3.16. 6.3.17. 6.3.18. 6.3.19. 6.3.20. 6.3.21. 6.3.22. 6.3.23. PWCTR3 (C2H): Power Control 3 (in Normal mode/ Full colors)....................................................................................... 94 PWCTR4 (C3H): Power Control 4 (in Idle mode/ 8-colors) ................................................................................................ 96 PWCTR5 (C4H): Power Control 5 (in Partial mode/ full-colors) ......................................................................................... 98 VMCTR1 (C5H): VCOM Control 1.................................................................................................................................... 100 VMCTR2 (C6H): VCOM Control 2.................................................................................................................................... 102 RDVMOF (C8H): Read the VCOM Offset Value NV memory .......................................................................................... 104 WRID2 (D1h): Write ID2 Value ......................................................................................................................................... 105 WRID3 (D2h): Write ID3 Value ......................................................................................................................................... 106 RDID4 (D3h): Read the ID4 value .................................................................................................................................... 107 NVFCTR1 (D9h): NV Memory Function Controller 1 ....................................................................................................... 108 NVFCTR2 (DEh): NV Memory Function Controller 2 ........................................................................................................110 NVFCTR3 (DFh): NV Memory Function Controller 3 ........................................................................................................111 GMCTRP1 (E0H): Gamma (`+'polarity for Red color) Correction Characteristics Setting.................................................112 GMCTRN1 (E1H): Gamma (`-'polarity for Red color) Correction Characteristics Setting .................................................114 3 NOV. 20, 2006 Preliminary Version: 0.2 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w 6.3.3. FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors) ............................................................................................. 83 w w 6.3. PANEL COMMAND DESCRIPTION ........................................................................................................................................................... 80 .m VSYNCON (ADH): VSYNC Interface ON ........................................................................................................................... 78 bt re SRGBOFF (AAH): Separate RGB Gamma OFF ................................................................................................................ 75 nd .co COLMOD (3AH): Interface Pixel Format ............................................................................................................................ 71 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.24. 6.3.25. 6.3.26. 6.3.27. GMCTRP2 (E2H): Gamma (`+'polarity) for Green color Correction Characteristics Setting .............................................116 GMCTRN2 (E3H): Gamma (`-'polarity) for Green color Correction Characteristics Setting ..............................................118 GMCTRP3 (E4H): Gamma (`+'polarity) for Blue color correction Characteristics Setting ................................................ 120 GMCTRN3 (E5H): Gamma (`-'polarity) for Blue color Correction Characteristics Setting................................................ 122 7. FUNCTION DESCRIPTION ..................................................................................................................................................................... 124 7.1. MCU & RGB INTERFACE ................................................................................................................................................................... 124 7.2. MPU INTERFACE ............................................................................................................................................................................... 126 7.2.1. Interface Type Selection........................................................................................................................................................ 126 7.2.2. 8080-Series Parallel interface(P68='0') ................................................................................................................................ 126 7.2.3. 6800-Series Parallel Interface (P68='1') ............................................................................................................................... 129 7.2.4. Serial Peripheral interface (SPI) ........................................................................................................................................... 132 7.2.5. Data Transfer Break and Recovery....................................................................................................................................... 134 7.2.7. Data Transfer Modes ............................................................................................................................................................ 137 7.3. MCU DATA COLOUR CODING ............................................................................................................................................................. 138 7.3.1. MCU Data Colour Coding for RAM data Write...................................................................................................................... 138 7.3.3. Serial Interface (IM2 = `0')..................................................................................................................................................... 154 7.4. RGB INTERFACE ................................................................................................................................................................................ 157 7.4.2. General Timing Diagram ....................................................................................................................................................... 158 7.4.5. RGB Interface Mode Set....................................................................................................................................................... 161 7.4.6. RGB Interface Timing Diagram ............................................................................................................................................. 162 7.4.7. RGB Data Color Coding........................................................................................................................................................ 173 7.5. DISPLAY DATA RAM ........................................................................................................................................................................... 176 7.5.1. Configuration......................................................................................................................................................................... 176 7.5.2. Memory to Display Address Mapping ................................................................................................................................... 177 7.5.3. Normal Display On or Partial Mode On, Vertical Scroll Off ................................................................................................... 180 7.5.4. Vertical Scroll Mode .............................................................................................................................................................. 183 7.5.5. Vertical Scroll Example ......................................................................................................................................................... 185 7.6. ADDRESS COUNTER........................................................................................................................................................................... 186 7.7. MEMORY DATA WRITE/ READ DIRECTION ............................................................................................................................................ 187 7.8. TEARING EFFECT OUTPUT LINE.......................................................................................................................................................... 189 7.8.1. Tearing Effect Line Modes .................................................................................................................................................... 189 7.8.2. Tearing Effect Line Timings ................................................................................................................................................... 190 7.8.3. Example 1: MPU Write is faster than panel read. ................................................................................................................. 191 7.8.4. Example 2: MPU write is slower than panel read. ................................................................................................................ 192 7.9. PRESET VALUES ................................................................................................................................................................................ 193 7.10. POWER ON/OFF SEQUENCE ............................................................................................................................................................. 193 7.10.1. 7.10.2. 7.10.3. Case 1 - RESX Line is held High or Unstable by Host at Power On ............................................................................... 193 Case 2 - RESX Line is Held Low by Host at Power On................................................................................................... 194 Uncontrolled Power Off .................................................................................................................................................... 194 7.11. POWER LEVEL DEFINITION ................................................................................................................................................................. 195 (c) ORISE Technology Co., Ltd. Proprietary & Confidential 4 NOV. 20, 2006 Preliminary Version: 0.2 w w 7.4.4. RGB Interface Bus Width set ................................................................................................................................................ 161 w 7.4.3. Updating Order on Display Active Area (Normal Display Mode On + Sleep Out)................................................................. 159 .m 7.4.1. General Description .............................................................................................................................................................. 157 bt re 7.3.2. MCU Data Colour Coding for RAM data Read ..................................................................................................................... 149 nd .co 7.2.6. Data Transfer Pause ............................................................................................................................................................. 136 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.11.1.Power Level .......................................................................................................................................................................... 195 7.11.2.Power Flow Chart ................................................................................................................................................................. 196 7.12. GAMMA CURVES ................................................................................................................................................................................ 197 7.13. RESET............................................................................................................................................................................................... 198 7.13.1. 7.13.2. 7.13.3. Reset Value ...................................................................................................................................................................... 198 Module Input/Output Pins ................................................................................................................................................. 201 Reset Timing..................................................................................................................................................................... 202 7.14. COLOUR DEPTH CONVERSION LOOK UP TABLES ................................................................................................................................. 203 7.14.1. 4096 and 65536 Colour to 262,144 Colour ...................................................................................................................... 203 7.15. SLEEP OUT-COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE .......................................................................... 207 7.15.1. 7.15.2. 7.15.3. 7.15.4. Register Loading Detection .............................................................................................................................................. 207 Functionality Detection ..................................................................................................................................................... 208 Display Glass Break Detection ......................................................................................................................................... 210 7.16. OSCILLATOR .......................................................................................................................................................................................211 7.17. SYSTEM COLCK GENERATOR ..............................................................................................................................................................211 7.19. SOURCE DRIVER.................................................................................................................................................................................211 7.20. GATE DRIVER .....................................................................................................................................................................................211 7.21. -CORRECTION FUNCTION .......................................................................................................................................................... 212 8.1. DC CHARACTERISTICAC CHARACTERISTIC (VDD=2.6V~3.0V, VDDIO = 1.6V~3.0V, TA = -40 ~ 85) ......................................... 216 8.2. AC TIMING CHARACTERISTICS ............................................................................................................................................................ 217 8.2.1. Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (8080-series MCU) ....................................................................... 217 8.3. PARALLEL INTERFACE CHARACTERISTICS 18, 16 ,9 OR 8-BITS BUS (6800-SERIES MCU) ...................................................................... 219 8.4. SERIAL INTERFACE CHARACTERISTICS (3-PIN SERIAL)......................................................................................................................... 220 9. PAD LOCATIONS ................................................................................................................................................................................... 221 9.1. PAD ASSIGNMENT............................................................................................................................................................................. 221 9.2. PAD LOCATIONS ................................................................................................................................................................................ 222 9.3. WIRING RESISTANCE.......................................................................................................................................................................... 229 10. DISCLAIMER........................................................................................................................................................................................... 231 10. REVISION HISTORY............................................................................................................................................................................... 232 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w 8. ELECTRICAL SPECIFICATIONS ........................................................................................................................................................... 216 w 7.22. VSYNC INTERFACE ........................................................................................................................................................................... 212 .m 7.20.1. Gate Driver ........................................................................................................................................................................211 bt 5 re 7.18. INSTRUCTION DECODER AND REGISTER...............................................................................................................................................211 nd .co Chip Attachment Detection ............................................................................................................................................... 209 m NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 528-CHANNEL DRIVER WITH SYSTEM-ON-CHIP (SOC) FOR COLOR AMORPHOUS TFT LCD 1. GENERAL DESCRIPTION The SPF54126B, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 176xRGBx220 in resolution which can be achieved by the designated RAM for graphic data. The 528-channel source driver has true 6-bit resolution, which generates 64 Gamma-corrected values by an internal D/A converter. The source driver of SPFD54126B adopts OP-AMP structure to enhance display quality and it cooperates with advanced circuitry techniques to reduce power consumption. The SPFD54126B is able to operate with low IO interface power supply up to 1.6V and incorporate with several charge pumps to generate various voltage levels that form an on-chip power management system for gate driver and common driver. System interfaces - High-speed interfaces to 8-, 9-, 16-, and 18-bit parallel ports - Serial Peripheral Interface (SPI) Interfaces for moving picture display - 6-, 16-, and 18-bit RGB interfaces Diverse RAM accessing for functional display - Window address function to display at any area on the screen via a moving picture display interface - Window address function to limit the data rewriting area and reduce data transfer - Moving and still picture can display at the same time - Vertical scrolling function - Partial screen display Power supply - Logic power supply voltage (VDD): 2.6 ~ 3.5 V - I/O interface supply voltage (VDDI): 1.6 ~ 3.6 V On-chip power management system - Power saving mode (standby / 8-color mode, etc) - Low power consumption OP-AMP structure for source driver. Built-in Charge Pump circuits - Source driver voltage level : 2 times (x2) of Vci1 - Gate driver voltage level (VGH, VGL) up to 6 times (x6) and minus 5 times (x-5) Vci1 Built-in internal oscillator and hardware reset Built-in One-Time-Programming (OTP) function for VCOM amplitude and VcomH voltage adjustment. Built-in separate three-gamma curves (RGB) controller to fine tune display quality. The built-in timing controller in SPFD54126B can support several display. SPFD54126B provides system interfaces, which include to configure system. Not only can the system interfaces be used to configure system, they can also access RAM at high speed for still and 18-bit RGB interfaces for picture movement display. The SPFD54126B also supports a function to display eight colors and a standby mode for power control consideration. picture display. In addition, the SPFD54126B incorporates 6, 16, 2. FEATURE One-chip solution for amorphous TFT-LCD. Supports resolution up to 176xRGBx220, incorporating a 528-channel source driver and a 220-channel gate driver Outputs 64 -corrected values using an internal true 6-bit resolution D/A converter to achieve 262K colors 528-channel source driver adopts OP-AMP structure Built-in 87120 bytes internal RAM Line Inversion AC drive / frame inversion AC drive w w w 8-/9-/16-/18-bit parallel interfaces and 9-bit serial interface (SPI), .m interfaces for the diverse request of medium or small size portable bt re nd .co 6 3. ORDERING INFORMATION Product Number SPFD54126B-C Package Type Chip Form With Gold Bump (c) ORISE Technology Co., Ltd. Proprietary & Confidential m NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 4. BLOCK DIAGRAM 4.1. Block Function S1 P68 DCX/SCL SDA IM[2:0] CSX RDX WRX S2 S527 S528 OTP Memory System Interface 6 Source Driver (528 channels) True 6-bit D/A Converter 6 6 6 Level Shifter (528 x 6bits) LUT D[17:0] DE PCLK VS HS 18 18 w TE RESX EXTC IDM GM[1:0] LCM[1:0] RCM[1:0] SRGB SMX SMY SHUT REV RL TB nd .co RGB Interface Graphics RAM 87120 bytes 6 6 6 6 Data Latch (176 x 3 x 6bits x2) m Shift Register (176 bits) 64 AVDD Gamma Voltage Generator GVDD re bt VDD VREF w Timing Signal Generator .m Regulator VCI1 VCOMH w VCI1 C11P/N C12P/N Gate Power Charge Pump AVDD VCOM VCOM VCOML VGL CLK VDDI Clock Generator C21P/N C22P/N C23P/N VGH Gate Driver VCL G[220:1] (c) ORISE Technology Co., Ltd. Proprietary & Confidential 7 NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 4.1.1. System Interface The SPFD54126B supports three high-speed system interfaces: 1. 80-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports. 2. 68-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports. 3. 3-pin 9-bits Serial Peripheral Interface (SPI). The SPFD54126B has a 16-bit index register (IR) and two 18-bit data registers, a write-data register (WDR) and a read-data register (RDR). The IR register is used to store index information from control registers. The WDR register is used to temporarily store data to be written for register control and internal GRAM. The RDR register is used to temporarily store data read from the GRAM. When graphic data is written to the internal GRAM from MCU/graphic engine, the data is first written to the WDR and then automatically written to the internal GRAM in internal operation. When graphic data read operation is executed, graphic data is read via the RDR from the internal GRAM. Therefore, the SPFD54126B executes the 2 read operation. nd 4.1.2. External Display Interface The SPFD54126B supports external RGB interface for picture movement display. optimum interface is selected for still / moving picture displayed on the screen. The SPFD54126B allows switching between one of the external display interfaces and the system interface via pin configuration so that the When the RGB interface is chosen, display operations are synchronized with external supplied signals, VSYNC, HSYNC, and DOTCLK. SPFD54126B features an Address Counter (AC) giving an address to the internal GRAM. The address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM. 4.1.4. Graphics RAM (GRAM) SPFD54126B features a 87120-byte (176 x 220x 18/8) Graphic RAM (GRAM). 4.1.5. Grayscale Voltage Generating Circuit SPFD54126B has true 6-bit resolution D/A converter, which generates 64 Gamma-corrected values and cooperates with OP-AMP structure to enhance display quality. The grayscale voltage can be adjusted by grayscale data set in the -correction register. "-Correction Function" section. For details, see the 4.1.6. Timing Controller SPFD54126B has a timing controller which can generate a timing signal for internal circuit operation such as gate output timing, RAM accessing timing, etc. 4.1.7. Oscillator (OSC) The SPFD54126B also features an internal oscillator to generate RC oscillation with an internal resistor. In standby mode, RC oscillation is halted to reduce power consumption. See "Oscillator" for details. 4.1.8. Source Driver Circuit SPFD54126B consists of a 528-output source driver circuit (S1 ~ S528). Data in the GRAM are latched when the 528 bit data is input. th The latched data controls the source driver and generates a drive waveform. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w 4.1.3. Address Counter (AC) .m Moreover, valid display data (DB17-0) is written to GRAM, which synchronized with signal (DE) enabling. bt 8 re nd .co m invalid data is first read out to the data bus when the SPFD54126B executes the 1 read operation. st Thus, valid data can be read out after NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 4.1.9. Gate Driver Circuit SPFD54126B consists of a 220-output gate driver circuit (G1~G220). The gate driver circuit outputs gate driver signals at either VGH or VGL level. 4.1.10. LCD Driving Power Supply Circuit The LCD driving power supply circuit generates the voltage levels AVDD, VGH, VGL and VCOM for driving an LCD. All this voltages can be adjusted by register setting. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 9 bt re nd .co m NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 5. SIGNAL DESCRIPTIONS Signal Pin No. I/O Connected with Function System Configuration Input Signal P68, IM2~0 4 I DGND/ VDDI Select system interface mode. P68 0 0 0 0 0 1 1 1 1 1 IM2 0 1 1 1 1 0 1 1 IM1 0 0 1 1 0 0 IM0 0 1 0 1 3-Pin Serial interface 8080 MCU 8-bits Parallel interface 8080 MCU 16-bits Parallel interface 8080 MCU 9-bits Parallel interface 8080 MCU 18-bits Parallel interface 3-Pin Serial interface 6800 MCU 8-bits Parallel interface 6800 MCU 16-bits Parallel interface 6800 MCU 9-bits Parallel interface 6800 MCU 18-bits Parallel interface Must connect to the GND or VDDI level when not used. RESX 1 I MPU or external RC circuit EXTC 1 I DGND/ VDDI Reset pin. This is an active low signal. w GM1~0 2 I DGND/ VDDI w w .m Extend command set access Low: Extend command set is not accessible. High: Extend command set is accessible. If this is not used. Open it (This pin is internally pull low). Resolution selection: GM1 0 0 1 1 GM0 0 1 0 1 Resolution 176*RGB*220 176*RGB*176 Reserved 176*RGB*132 RCM1~0 2 I DGND/ VDDI Interface selection: RCM1 0 0 1 1 RCM0 0 1 0 1 Interface MCU Interface MCU Interface RGB Interface RGB Interface IDM 1 I MCU In RGB interface mode: (a) Low: Normal Display. (b) High: Idle Mode (8-color mode). This pin can be only used when RGB mode is selected. LCM 2 I DGND/ VDDI Liquid Crystal Type selection: LCM1 0 0 LCM0 0 1 LC type selection Normally black type1 Normally white type1 (c) ORISE Technology Co., Ltd. Proprietary & Confidential bt 10 re nd .co 1 1 1 0 1 1 1 m 0 - Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Signal Pin No. I/O Connected with Function 1 1 0 1 Normally black type2 Normally white type2 SRGB 1 I DGND/ VDDI RGB arrangement selection: RGB 0 0 1 1 SRGB 0 1 0 1 RGB filter order for CF default setting S1, S2, S3 fit `R', `G', `B S1, S2, S3 fit `B', `G', `R S1, S2, S3 fit `B', `G', `R S1, S2, S3 fit `R', `G', `B The RGB is the D4 for Command 36H (a) Low: Display On. (b) High: Display Off. REV 1 I DGND/ VDDI This pin can be only used when RGB mode is selected. Data reverse for source driver selection when RGB mode is selected. (a) Low: Reverse Off. (b) High: Reserve On. SMX 1 I DGND/ VDDI This pin can be only used when RGB mode is selected. Source driver output direction selection: SMX 0 1 Source output direction S1 => S528 S528=>S1 w SMY 1 I DGND/ VDDI w .m Gate driver output direction selection: SMY 0 1 GM="00" G1 =>G220 G220=>G1 GM="01" G1=>G176 G176=>G1 GM="11" G1=>G132 G132=>G1 RL 1 I w DGND/ VDDI Source driver output direction selection: SMX 0 0 1 1 RL 0 1 0 1 Source output direction S1 => S528 S528 => S1 S528 => S1 S1 => S528 This pin can be only used when RGB mode is selected. TB 1 I DGND/ VDDI Gate driver output direction selection: SMY 0 0 1 1 TB 0 1 0 1 GM="00" G1 =>G220 G220 =>G1 G220 =>G1 G1 =>G220 GM="01" G1=>G176 G176 =>G1 G176 =>G1 G1=>G176 GM="11" G1=>G132 G132=>G1 G132=>G1 G1=>G132 This pin can be only used when RGB mode is selected. Interface input Signals CSX 1 I MPU Chip select signal. Low: the SPFD54126B is accessible (c) ORISE Technology Co., Ltd. Proprietary & Confidential 11 Apr. 25, 2006 Preliminary Version: 0.1 bt re nd .co m SHUT 1 I DGND/ VDDI Display on/off selection when RGB mode is selected. Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Signal Pin No. I/O Connected with Function High: the SPFD54126B is not accessible This pin has can be permanently fixed "Low" in MCU interface mode only. D/CX (SCL) 1 I MPU Display data / Command selection pin in parallel interface Low: Command data High: Display data In SPI I/F, this is used as SCL pin. Must connect to the GND or VDDI level when not used. WRX (R/WX) 1 I MPU (A) In 80-system interface mode, a write strobe signal can be input via this pin and initializes a write operation when the signal is low. (B) In 68-system interface mode, a write or read control signal can be input via Must connect to the GND or VDDI level when not used. RDX (E) 1 I MPU (A) In 80-system interface mode, a read strobe signal can be input via this pin and initializes a read operation when the signal is low. (B) In 68system interface mode, a strobe signal can be input via this pin and initializes a write or read operation when the signal is low. SPI_CSX 1 I MPU Must connect to the GND or VDDI level when not in use. (A) When RCM [1:0] = `01' Chip select pin for SPI (Low active) (B) When RCM [1:0] = `00' or `1X' this pin and initializes a write or read operation. w w SCL 1 I MPU w SDA 1 I/O MPU DB0-DB17 2*18 I/O MPU VS HS DE 1 1 1 I I I MPU MPU MPU (c) ORISE Technology Co., Ltd. Proprietary & Confidential .m If not used, please fix this pin at VDDI or DGND level. (A) When RCM [1:0] = `01' Serial clock signal pin for SPI (B) When RCM [1:0] = `00' or `1X' If not used, please fix this pin at VDDI or DGND level. (A) When RCM [1:0] = `01' or `1X' Serial input/ output signal in serial I/F mode. The data is input on the rising edge of the SCL signal. The data is output on the falling edge of the SCL signal. (B) When RCM [1:0] = `00' If not used, please fix this pin at VDDI or DGND level. (A) When RCM [1:0] = `1X' (RGB I/F), D[17:0] are used for RGB interface data bus (B) When RCM [1:0] = `00' (MCU I/F), D[17:0] are used to MCU parallel interface data bus In SPI I/F, D0 is used as Serial input/ output signal. In SPI I/F, D[17:1] not used, please fix this pin at VDDI or DGND level. (C) When RCM [1:0] = `01' (MCU I/F), D[17:0] are used for MCU interface data bus In SPI I/F, D[17:0] not used, please fix this pin at VDDI or DGND level. In RGB I/F or VSYNC I/F mode, served as a vertical synchronize signal input Must connect to the VDDI or DGND level when not in use. In RGB I/F mode, served as a horizontal synchronized signal input Must connect to the VDDI or DGND level when not in use. In RGB I/F mode, polarity of DE signal is synchronized with valid graphic data input. High: Valid data on DB17-DB0 Low: Invalid data on DB17-DB0 12 Apr. 25, 2006 Preliminary Version: 0.1 bt This pin is not used, and fix at VDDI or DGND level. This pin is not used, and fix at VDDI or DGND level. This pin is not used, and fix at VDDI or DGND level. re nd .co m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Signal Pin No. I/O Connected with Function Must connect to the VDDI or DGND level when not in use. PCLK 1 I MPU In RGB I/F mode, served as a pixel clock signal. Must connect to the VDDI or DGND level when not in use. Charge Pump and Power Supply Signal C11P/N, C12P/N C21P/N, C22P/N C23P/N VCI1 4/4 4/4 3/3 3/3 3/3 5 O Stabilizing capacitor AVDD VGH VGL VCL VCC 6 3 3 3 5 5 4 O O O O O O I/O Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor VREF GVDD Stabilizing capacitor An internal reference voltage level, which is regulated from VDD. The GND. amplitude of VCI1 is from VDD-GND. Place a stabilizing capacitor between Output 2x VCI1 voltage level from the step-up circuit 1. Place a stabilizing capacitor between GND. AVDD = 4.5 ~ 5.5V An output voltage from the step-up circuit 2x, 4x ~ 6x of the VCI1 level. Connect with a stabilizing capacitor. Connect with a stabilizing capacitor. An output voltage from the step-up circuit 2, -1x of the VCI1 level. Connect with a stabilizing capacitor. An output voltage from the step-up circuit -2x, -3x ~ -5x of the VCI1 level. Step-up capacitor Connect boost capacitors for the internal DC/DC converter circuit to these pins. Leave the pins open when DC/DC converter circuits are not used. w w w Stabilizing capacitor Source/Gate Driver and VCOM Signals G1~G220 S1~S528 220 528 O O O LCD LCD TFT panel common electrode VcomH VcomL 4 4 O O Stabilizing capacitor Stabilizing capacitor or open VDDIO DGNDO VDD VDDI 5 10 10 8 12 O O I I Stabilizing capacitor Stabilizing capacitor DGND Digital ground pin. 13 Apr. 25, 2006 Preliminary Version: 0.1 Power supply Input for I/O system VDDI input voltage for control pins using DGND input voltage for control pins using Power supply Input for analog and booster system Output the low level of VCOM voltage. Connect with a capacitor to stabilize. Output gate driver signals, which has the swing from VGH to VGL Output source driver signals. The D/A converted 64-gray-scale analog voltage is output. VCOM 6 Output a square wave signal with the swing from VcomH - VcomL to the common electrode of TFT panel. The alternating cycle can be set to frame inversion or 1-line inversion. Output the high level of VCOM voltage. Connect with a capacitor to stabilize. (c) ORISE Technology Co., Ltd. Proprietary & Confidential .m Reference voltage for Internal logic block Connect with a stabilizing capacitor Reference voltage for power block Connect with a stabilizing capacitor. Output source driver grayscale reference voltage level. bt re nd .co m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Signal AGND Misc. Signal DRV FB TE 2 1 1 O I O MPU Drive signal for the power transistor of the LED booster converter LED booster regulator feedback input. Connect feedback resistive divider to GND. FB threshold is 0.6V normal. Tearing effect output pin to synchronies MCU to frame writing, activated by S/W command. When this pin is not activated (TE function OFF), this pin is DGND level. Power supply input for OTP function This pin is used for glass break detection This pin is used for glass break detection Pin No. 15 I/O Connected with Function Analog ground pin. VOTP PADA0 PADB0 PADA1/PADB1 PADA2/PADB2 PADA3/PADB3 PADA4/PADB4 TEST Dummy PREG OSC 2 1 1 8 I I O 18 22 1 1 T D D I Test pin. If not used, please open this pin. Dummy pin. If not used, please open this pin. If not used, please open this pin. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 14 bt External oscillator frequency input pin for oscillator testing re Dummy pin. If not used, please open this pin. nd .co m This pin is used for chip attachment detection Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6. INSTRUCTIONS 6.1. Outline The SPFD54126B supports 18-bit data bus interface to configure system via accessing command register. When the command register is executed, sending the command information to specify which index register would be accessed and following the data to that control register. Moreover, register accessing operation should cooperate with DC/X, WRX, RDX signal for SPFD54126B to recognize the control instruction. And command instruction can be accomplished using all system interfaces (18-bit, 16-bit, 9-bit, 8-bit 80- or 68-system and SPI).. 6.1.1. System Function Command List and Description Table 5.1.1 list all the system function command. After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer "RESET TABLE" section). Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTR Diagnostic Result (0Fh) of these commands are updated immediately both in Sleep In mode and Sleep Out mode. (0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh) and Read Display Self Table 6.1.1 System Function command List (1) Instruction D/CX WRX RDX D17-8 NOP SWRESET 0 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 RDD MADCTR RDD COLMOD 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 - nd .co D2 0 0 1 D1 0 0 0 D0 0 1 0 D1 D0 m (Hex) RDDID RDDST RDDPM (00h) No Operation (01h) Software reset (04h) Read Display ID Dummy read ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID1 read ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID2 read ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 ID3 read 0 0 0 0 1 0 0 1 (09h) Read Display Status Dummy read BSTON MY MX MV ML RGB ST25 ST24 ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON VSSON ST14 INVON ST12 ST11 DISON TEON GCS2 GCS1 GCS0 TELOM HSON VSON PCKON DEON ST0 0 0 0 0 1 0 1 0 (0Ah) Read Display Power Mode Dummy read w w w .m bt re Function BSTON IDMON PTLON SLPOUT NORON DISON - RDDIM RDDSM RDDSDR (0Bh) Read Display MADCTR Dummy read MX MY MV ML RGB D2 D1 D0 0 0 0 0 1 1 0 0 (0Ch) Read Display Pixel Format Dummy read D7 D6 D5 D4 D3 IFPF2 IFPF1 IFPF0 0 0 0 0 1 1 0 1 (0Dh) Read Display Image Mode Dummy read VSSON D6 INVON D4 D3 GCS2 GCS1 GCS0 0 0 0 0 1 1 1 0 (0Eh) Read Display Signal Mode Dummy read TEON TELOM HSON VSON PCKON DEON D1 D0 0 0 0 0 1 1 1 1 (0Fh) Read Display Self-diagnostic result Dummy read RELD FUND ATTD BRD D3 D2 D1 D0 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 1 - "-": Dont care, can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 15 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.1 System Function command List (2) Instruction D/CX WRX RDX D17-8 SLPIN SLPOUT PTLON NORON INVOFF INVON GAMSET DISPOFF DISPON 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D17-8 D17-8 D7 0 0 0 0 0 0 0 GC7 0 0 0 XS15 XS7 XE15 XE7 0 YS15 YS7 YE15 YE7 0 D7 0 D7 0 R007 : Ra7 G007 : Gb7 B007 : Bc7 D6 0 0 0 0 0 0 0 GC6 0 0 0 XS14 XS6 XE14 XE6 0 YS14 YS6 YE14 YE6 0 D6 0 D6 0 R006 : Ra6 G006 : Gb6 B006 : Bc6 D5 0 0 0 0 1 1 1 GC5 1 1 1 XS13 XS5 XE13 XE5 1 YS13 YS5 YE13 YE5 1 D5 1 D5 1 R005 : Ra5 G005 : Gb5 B005 : Bc5 D4 1 1 1 1 0 0 0 GC4 0 0 0 XS12 XS4 XE12 XE4 0 YS12 YS4 YE12 YE4 0 D3 0 0 0 0 0 0 0 GC3 1 1 1 XS11 XS3 XE11 XE3 1 YS11 YS3 YE11 YE3 1 D2 0 0 0 0 0 0 1 GC2 0 0 0 XS10 XS2 XE10 XE2 0 YS10 YS2 YE10 YE2 1 D1 0 0 1 1 0 0 1 GC1 0 0 1 XS9 XS1 XE9 XE1 1 YS9 YS1 YE9 YE1 0 D1 1 D1 0 R001 : Ra1 G001 : Gb1 B001 : Bc1 D0 0 1 0 1 0 1 0 GC0 0 1 0 XS8 XS0 XE8 XE0 1 YS8 YS0 YE8 YE0 0 (Hex) (10h) (11h) (12h) (13h) (20h) (21h) (26h) Function Sleep in & booster off Sleep out & booster on Partial mode on Partial off (Normal) Display inversion off (normal) Display inversion on Gamma curve select (28h) Display off (29h) Display on (2Ah) Column address set X address start: 0 XS 0xAF X address end: XS XE 0xAF nd .co D2 1 D2 1 R002 : Ra2 G002 : Gb2 B002 : Bc2 CASET re D3 1 D3 1 R003 : Ra3 G003 : Gb3 B003 : Bc3 16 RASET bt D4 0 D4 0 R004 : Ra4 G004 : Gb4 B004 : Bc4 .m RAMWR RGBSET "-": Don't care, can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w RAMHD D0 Write data 0 (2Eh) Memory read Dummy read D0 Read data 1 (2Dh) LUT for 4k,65k , 262K color display R000 Red tone 0 : :Ra0 Red tone "31" G000 Green tone 0 : :Gb0 Green tone "63" B000 Blue tone 0 : :Bc0 Blue tone "31" m (2Ch) (2Bh) Row address set Y address start: 0 YS 0xDB Y address end: YS YE 0xDB Memory write Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.1 System Function command List (3) Instruction D/CX WRX RDX D17-8 0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0 (Hex) Function (30h) Partial start/end address set PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8 Partial start address (0,1,2, .., 219) PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8 PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 PTLAR Partial end address (0,1,2, .., 219) (33h) Scroll area set Top fixed area (0,1,2, .., 220) Vertical scroll area (0,1,2, ..,220) Bottom fixed area (0,1,2, ..,220) 0 0 1 1 0 0 1 1 TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8 TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 VSA9 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 SCRLAR TEOFF TEON MADCTR SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 COLMOD RDID1 RDID3 SRGBOFF SRGBON VSUNCOFF VDUNCON VSCTRI w RDID2 w w .m bt 0 0 0 1 1 1 IDMOFF IDMON (38h) Idle mode off (39h) Idle mode on (3Ah) Interface pixel format IFPF2 IFPF1 IFPF0 0 0 0 0 0 Interface format 1 1 0 1 1 0 1 0 (DAh) Read ID1 Dummy read ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 Read parameter 1 1 0 1 1 0 1 1 (DBh) Read ID2 Dummy read ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 Read parameter 1 1 0 1 1 1 0 0 (DCh) Read ID3 Dummy read ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Read parameter 1 0 1 0 1 0 1 0 (AAh) Separate RGB function OFF 1 0 1 0 1 0 1 1 (ABh) Separate RGB function ON 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 re 1 1 1 0 0 0 17 VSCSAD (34h) Tearing effect line off (35h) Tearing effect mode set & on 0 0 0 0 0 0 0 TELOM M="0": Mode1, M="1": Mode2 0 0 1 1 0 1 1 0 (36h) Memory data access control MY MX MV ML RGB 0 0 0 0 0 1 1 0 1 1 1 (37h) Scroll start address of RAM SSA15 SSA14 SSA13 SSA12 SSA11 SSA10 SSA9 SSA8 SSA = 0, 1, 2, ..., 219 VSFP3 VSFP2VSFP1VSFP0 VSBP3 VSBP2 VSBP1 VSBP0 "-": Don't care, can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 m (ACh) VSYNC interace function OFF (ADh) VSYNC interace function ON (AEh) VSYNC interace control VS porch setting Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.1.2. Panel Function Command List and Description Table 6.1.2 list all the panel function command. Panel function command is only accessible when EXTC is pulled high state (by VDDIO). Table 6.1.2 Panel Function command List (1) Instruction D/CX WRX RDX D17-8 RGBCTR 0 1 0 1 FRMCTR1 1 1 0 1 FRMCTR2 1 1 0 1 FRMCTR3 1 1 INVCTR RGB PRCTR 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 0 D7 1 0 1 D6 0 0 0 D5 1 0 1 D4 1 ICM 1 D3 0 DP D2 0 EP D1 0 D0 0 (Hex) Function (B0h) Set RGB signal control (B1h) In normal mode (Full colors) FP0: Front porch in normal mode BP0: Back porch in normal mode RTN0: Number of clock / one line HSP VSP ICM: RGB data ascess select DP,HSP,VSP:PCLK,HS,VS polarity set DISSET5 1 0 0 0 0 0 0 0 0 1 FP0 FP0 FP0 FP0 [3] [2] [1] [0] BP0 BP0 BP0 BP0 [3] [2] [1] [0] RTN0 RTN0 RTN0 RTN0 [3] [2] [1] [0] 1 1 0 0 1 0 FP1 FP1 FP1 FP1 [3] [2] [1] [0] BP1 BP1 BP1 BP1 [3] [2] [1] [0] RTN1 RTN1 RTN1 RTN1 [3] [2] [1] [0] 1 1 0 0 1 1 FP2 FP2 FP2 FP2 [3] [2] [1] [0] BP2 BP2 BP2 BP2 [3] [2] [1] [0] RTN2 RTN2 RTN2 RTN2 [3] [2] [1] [0] 1 1 0 1 0 0 0 0 0 NLA NLB NLC 1 1 0 1 0 1 VBP VBP VBP VBP [3] [2] [1] [0] 1 1 0 1 1 1 NO1 NO0 SDT1 STD0 EQ1 EQ0 nd .co PT0 m (B2h) In Idle mode (8-colors) FP1: Front porch in idle mode BP1: Back porch in idle mode RTN1: Number of clock / one line re 18 (B3h) In partial mode + Full colors FP2: Front porch in partial mode BP2: Back porch in partial mode RTN2: Number of clock / one line .m bt 0 w (B4h) Display inversion control NLA, NLB, NLC: set inversion w (B5h) RGB I/F Blanking porch setting Vertical back porch in RGB mode NO: the amount of non-overlap SDT: set amount of source delay PT: No display area source/ VCOM/ Gate output control EQ: set EQ period w (B6h) Display function setting 0 PTG1 PTG0 PT1 "-": Don't care, can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.2 Panel Function Command List (2) Instruction D/CX WRX RDX D17-8 PWCTR1 0 1 1 0 1 0 1 1 0 1 1 PWCTR5 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 1 0 0 1 0 1 0 0 1 0 D6 0 0 0 0 0 0 0 0 0 0 D5 1 0 0 1 0 1 0 0 1 0 D4 D3 D2 D1 D0 (Hex) 1 0 0 0 0 VRH4 VRH3 VRH2 VRH1 VRH0 0 0 VC2 VC1 VC0 1 0 0 0 1 0 0 BT2 BT1 BT0 1 0 0 1 0 0 0 APA2 APA1 APA0 0 0 DCA2 DCA1 DCA0 1 0 0 1 1 0 0 APB2 APB1 APB0 Function (C0h) Power control setting VRH: Set the GVDD voltage VC : Set the VCI1 voltage Power control setting (C1h) BT: set AVDD/VCL/ VGH/ VGL voltage (C2h) n normal mode (Full colors) PWCTR2 PWCTR3 PWCTR4 VMCTR1 1 0 1 nVM 0 0 1 1 0 nd .co 1 1 0 D2 0 0 D1 0 1 D0 1 0 1 1 1 1 0 1 APA: adjust the operational amplifier DCA: adjust the booster circuit for Idle mode (C3h) In Idle mode (8-colors) APB: adjust the operational amplifier DCB: adjust the booster circuit for Idle mode 0 0 0 0 0 DCB2 DCB1 DCB0 I 1 0 1 1 0 1 0 0 (C4h) In partial mode + Full colors APC: adjust the operational amplifier 0 0 0 0 0 APC2 APC1 APC0 DCC: adjust the booster circuit for Idle mode 0 0 0 0 0 DCC2 DCC1 DCC0 1 0 1 1 0 1 0 1 (C5h) VCOM control 1 nVM: VCOM input select VMH: VCOMH voltage control nVM VMH6 VMH 5 VMH4 VMH3 VMH2 VMH1 VMH0 m (C6h) (Hex) nVM VMF6 VMF5 VMF4 VMF3 VMF2 VMF1 VMF0 "-": Don't care, can be set to VDDI or DGND level Instruction D/CX WRX RDX D17-8 WRID2 0 1 0 WRID3 1 0 1 1 1 1 1 0 0 NVCTR2 NVCTR3 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - w Table 6.1.2 Panel Function Command List (3) D7 1 1 1 w D6 1 1 .m D5 0 0 bt D4 1 1 D3 0 0 1 1 1 1 19 RVMOF CTR 0 1 1 1 0 0 0 (C8h) VCOM control 4 RVMF RVMF RVMF RVMF RVMF RVMF RVMF Read the VMOF value form NV memory 6 5 4 3 2 1 0 re VMCTR2 VMA5 VMA4 VMA3 VMA2 VMA1 VMA0 VCOM control 2 VMA: VCOMAC voltage control w Function (D1h) Panel version code ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Write ID2 value to NV memory Set the LCM version code at ID2 (D2h) Driver maker Project code Write ID3 value to NV memory Set the project code at ID3 RDID4 NVCTR1 1 1 0 1 0 0 1 1 (D3h) IC Vender Coder Dummy read ID417 ID416 ID415 ID414 ID413 ID412 ID411 ID410 ID41:IC Vender Coder ID427 ID426 ID425 ID424 ID423 ID422 ID421 ID420 ID42: IC Part Number Coder ID43 & ID44: Chip version coder ID437 ID436 ID435 ID434 ID43 ID432 ID431 ID430 ID447 ID446 ID445 ID444 ID443 ID442 ID441 ID440 1 1 0 1 1 0 0 1 (D9h) NV memory function controller 1 1 1 1 1 0 0 Please refer to `OTP programming procedure' for details. (DEh) NV memory function controller 2 Please refer to `OTP programming procedure' for details. (DFh) NV memory function controller 3 Please refer to `OTP programming procedure' for details. "-": Don't care, can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.2 Panel Function Command List (4) Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 R_PVR1V1[5] R_PVR1V2[5] R_PVR1V61[5] R_PVR1V62[5] - D4 0 R_PVR1V0[4] R_PVR1V1[4] R_PVR1V2[4] R_PVR1V61[4] R_PVR1V62[4] R_PVR1V63[4] R_PVR2V13[4] R_PVR2V50[4] - D3 0 R_PVR1V0[3] R_PVR1V1[3] R_PVR1V2[3] R_PVR1V61[3] R_PVR1V62[3] R_PVR1V63[3] R_PVR2V13[3] R_PVR2V50[3] R_PVR3V4[3] R_PVR3V8[3] R_PVR3V20[3] R_PVR3V27[3] R_PVR3V36[3] R_PVR3V43[3] R_PVR3V55[3] R_PVR3V59[3] D2 0 R_PVR1V0[2] R_PVR1V1[2] R_PVR1V2[2] R_PVR1V61[2] R_PVR1V62[2] R_PVR1V63[2] R_PVR2V13[2] R_PVR2V50[2] R_PVR3V4[2] R_PVR3V8[2] R_PVR3V20[2] R_PVR3V27[2] R_PVR3V36[2] R_PVR3V43[2] R_PVR3V55[2] R_PVR3V59[2] D1 0 R_PVR1V0[1] R_PVR1V1[1] R_PVR1V2[1] R_PVR1V61[1] R_PVR1V62[1] R_PVR1V63[1] R_PVR2V13[1] R_PVR2V50[1] R_PVR3V4[1] R_PVR3V8[1] R_PVR3V20[1] R_PVR3V27[1] R_PVR3V36[1] R_PVR3V43[1] R_PVR3V55[1] R_PVR3V59[1] D0 0 R_PVR1V0[0] R_PVR1V1[0] R_PVR1V2[0] R_PVR1V61[0] R_PVR1V62[0] R_PVR1V63[0] R_PVR2V13[0] R_PVR2V50[0] R_PVR3V4[0] R_PVR3V8[0] R_PVR3V20[0] R_PVR3V27[0] R_PVR3V36[0] R_PVR3V43[0] R_PVR3V55[0] R_PVR3V59[0] (Hex) Function GAMCTRP1 1 1 1 1 1 1 1 1 1 R+ Gamma (E0h) adjustment "-": Don't care, can be set to VDDI or DGND level 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 - 1 - .m Instruction D/CX WRX RDX D17-8 D7 D6 D5 1 - bt D4 0 Table 6.1.2 Panel Function Command List (5) re D3 0 R_NVR1V0[3] R_NVR1V1[3] R_NVR1V2[3] R_NVR1V61[3] R_NVR1V62[3] R_NVR1V63[3] R_NVR2V13[3] R_NVR2V50[3] R_NVR3V4[3] R_NVR3V8[3] R_NVR3V20[3] R_NVR3V27[3] R_NVR3V36[3] R_NVR3V43[3] R_NVR3V55[3] R_NVR3V59[3] nd .co D2 0 R_NVR1V0[2] R_NVR1V1[2] R_NVR1V2[2] R_NVR1V61[2] R_NVR1V62[2] R_NVR1V63[2] R_NVR2V13[2] R_NVR2V50[2] R_NVR3V4[2] R_NVR3V8[2] R_NVR3V20[2] R_NVR3V27[2] R_NVR3V36[2] R_NVR3V43[2] R_NVR3V55[2] R_NVR3V59[2] m D1 0 R_NVR1V0[1] R_NVR1V1[1] R_NVR1V2[1] R_NVR1V61[1] R_NVR1V62[1] R_NVR1V63[1] R_NVR2V13[1] R_NVR2V50[1] R_NVR3V4[1] R_NVR3V8[1] R_NVR3V20[1] R_NVR3V27[1] R_NVR3V36[1] R_NVR3V43[1] R_NVR3V55[1] R_NVR3V59[1] D0 1 R_NVR1V0[0] R_NVR1V1[0] R_NVR1V2[0] R_NVR1V61[0] R_NVR1V62[0] R_NVR1V63[0] R_NVR2V13[0] R_NVR2V50[0] R_NVR3V4[0] R_NVR3V8[0] R_NVR3V20[0] R_NVR3V27[0] R_NVR3V36[0] R_NVR3V43[0] R_NVR3V55[0] R_NVR3V59[0] (Hex) Function R_NVR1V0[4] w - R_NVR1V1[5] R_NVR1V2[5] R_NVR1V1[4] R_NVR1V2[4] R_NVR1V61[4] R_NVR1V62[4] R_NVR1V63[4] R_NVR2V13[4] R_NVR2V50[4] - w w R_NVR1V61[5] R_NVR1V62[5] GAMCTRN1 1 1 1 1 1 1 1 1 1 R- Gamma (E1h) adjustment "-": Don't care, can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 20 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.2 Panel Function Command List (6) Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 G_PVR1V1[5] G_PVR1V2[5] G_PVR1V61[5] G_PVR1V62[5] - D4 0 G_PVR1V0[4] G_PVR1V1[4] G_PVR1V2[4] G_PVR1V61[4] G_PVR1V62[4] G_PVR1V63[4] G_PVR2V13[4] G_PVR2V50[4] - D3 0 G_PVR1V0[3] G_PVR1V1[3] G_PVR1V2[3] G_PVR1V61[3] G_PVR1V62[3] G_PVR1V63[3] G_PVR2V13[3] G_PVR2V50[3] G_PVR3V4[3] G_PVR3V8[3] G_PVR3V20[3] G_PVR3V27[3] G_PVR3V36[3] G_PVR3V43[3] G_PVR3V55[3] G_PVR3V59[3] D2 0 G_PVR1V0[2] G_PVR1V1[2] G_PVR1V2[2] G_PVR1V61[2] G_PVR1V62[2] G_PVR1V63[2] G_PVR2V13[2] G_PVR2V50[2] G_PVR3V4[2] G_PVR3V8[2] G_PVR3V20[2] G_PVR3V27[2] G_PVR3V36[2] G_PVR3V43[2] G_PVR3V55[2] G_PVR3V59[2] D1 0 G_PVR1V0[1] G_PVR1V1[1] G_PVR1V2[1] G_PVR1V61[1] G_PVR1V62[1] G_PVR1V63[1] G_PVR2V13[1] G_PVR2V50[1] G_PVR3V4[1] G_PVR3V8[1] G_PVR3V20[1] G_PVR3V27[1] G_PVR3V36[1] G_PVR3V43[1] G_PVR3V55[1] G_PVR3V59[1] D0 0 G_PVR1V0[0] G_PVR1V1[0] G_PVR1V2[0] G_PVR1V61[0] G_PVR1V62[0] G_PVR1V63[0] G_PVR2V13[0] G_PVR2V50[0] G_PVR3V4[0] G_PVR3V8[0] G_PVR3V20[0] G_PVR3V27[0] G_PVR3V36[0] G_PVR3V43[0] G_PVR3V55[0] G_PVR3V59[0] (Hex) Function GAMCTRP1 1 1 1 1 1 1 1 1 1 G+ Gamma (E2h) adjustment "-": Don't care, can be set to VDDI or DGND level Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 - bt D4 0 Table 6.1.2 Panel Function Command List (7) 1 - re D3 0 G_NVR1V0[3] G_NVR1V1[3] G_NVR1V2[3] G_NVR1V61[3] G_NVR1V62[3] G_NVR1V63[3] G_NVR2V13[3] G_NVR2V50[3] G_NVR3V4[3] G_NVR3V8[3] G_NVR3V20[3] G_NVR3V27[3] G_NVR3V36[3] G_NVR3V43[3] G_NVR3V55[3] G_NVR3V59[3] nd .co D2 0 G_NVR1V0[2] G_NVR1V1[2] G_NVR1V2[2] G_NVR1V61[2] G_NVR1V62[2] G_NVR1V63[2] G_NVR2V13[2] G_NVR2V50[2] G_NVR3V4[2] G_NVR3V8[2] G_NVR3V20[2] G_NVR3V27[2] G_NVR3V36[2] G_NVR3V43[2] G_NVR3V55[2] G_NVR3V59[2] m D1 0 G_NVR1V0[1] G_NVR1V1[1] G_NVR1V2[1] G_NVR1V61[1] G_NVR1V62[1] G_NVR1V63[1] G_NVR2V13[1] G_NVR2V50[1] G_NVR3V4[1] G_NVR3V8[1] G_NVR3V20[1] G_NVR3V27[1] G_NVR3V36[1] G_NVR3V43[1] G_NVR3V55[1] G_NVR3V59[1] D0 1 G_NVR1V0[0] G_NVR1V1[0] G_NVR1V2[0] G_NVR1V61[0] G_NVR1V62[0] G_NVR1V63[0] G_NVR2V13[0] G_NVR2V50[0] G_NVR3V4[0] G_NVR3V8[0] G_NVR3V20[0] G_NVR3V27[0] G_NVR3V36[0] G_NVR3V43[0] G_NVR3V55[0] G_NVR3V59[0] (Hex) Function w - G_NVR1V1[5] G_NVR1V2[5] w G_NVR1V61[5] G_NVR1V62[5] w .m G_NVR1V0[4] G_NVR1V1[4] G_NVR1V2[4] G_NVR1V61[4] G_NVR1V62[4] G_NVR1V63[4] G_NVR2V13[4] G_NVR2V50[4] - GAMCTRN1 1 1 1 1 1 1 1 1 1 G- Gamma (E3h) adjustment "-": Don't care, can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 21 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.2 Panel Function Command List (8) Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 B_PVR1V1[5] B_PVR1V2[5] B_PVR1V61[5] B_PVR1V62[5] - D4 0 B_PVR1V0[4] B_PVR1V1[4] B_PVR1V2[4] B_PVR1V61[4] B_PVR1V62[4] B_PVR1V63[4] B_PVR2V13[4] B_PVR2V50[4] - D3 0 B_PVR1V0[3] B_PVR1V1[3] B_PVR1V2[3] B_PVR1V61[3] B_PVR1V62[3] B_PVR1V63[3] B_PVR2V13[3] B_PVR2V50[3] B_PVR3V4[3] B_PVR3V8[3] B_PVR3V20[3] B_PVR3V27[3] B_PVR3V36[3] B_PVR3V43[3] B_PVR3V55[3] B_PVR3V59[3] D2 0 B_PVR1V0[2] B_PVR1V1[2] B_PVR1V2[2] B_PVR1V61[2] B_PVR1V62[2] B_PVR1V63[2] B_PVR2V13[2] B_PVR2V50[2] B_PVR3V4[2] B_PVR3V8[2] B_PVR3V20[2] B_PVR3V27[2] B_PVR3V36[2] B_PVR3V43[2] B_PVR3V55[2] B_PVR3V59[2] D1 0 B_PVR1V0[1] B_PVR1V1[1] B_PVR1V2[1] B_PVR1V61[1] B_PVR1V62[1] B_PVR1V63[1] B_PVR2V13[1] B_PVR2V50[1] B_PVR3V4[1] B_PVR3V8[1] B_PVR3V20[1] B_PVR3V27[1] B_PVR3V36[1] B_PVR3V43[1] B_PVR3V55[1] B_PVR3V59[1] D0 0 B_PVR1V0[0] B_PVR1V1[0] B_PVR1V2[0] B_PVR1V61[0] B_PVR1V62[0] B_PVR1V63[0] B_PVR2V13[0] B_PVR2V50[0] B_PVR3V4[0] B_PVR3V8[0] B_PVR3V20[0] B_PVR3V27[0] B_PVR3V36[0] B_PVR3V43[0] B_PVR3V55[0] B_PVR3V59[0] (Hex) Function GAMCTRP1 1 1 1 1 1 1 1 1 1 B+ Gamma (E4h) adjustment "-": Don't care, can be set to VDDI or DGND level Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 - bt D4 0 Table 6.1.2 Panel Function Command List (9) 1 - re D3 0 B_NVR1V0[3] B_NVR1V1[3] B_NVR1V2[3] B_NVR1V61[3] B_NVR1V62[3] B_NVR1V63[3] B_NVR2V13[3] B_NVR2V50[3] B_NVR3V4[3] B_NVR3V8[3] B_NVR3V20[3] B_NVR3V27[3] B_NVR3V36[3] B_NVR3V43[3] B_NVR3V55[3] B_NVR3V59[3] nd .co D2 0 B_NVR1V0[2] B_NVR1V1[2] B_NVR1V2[2] B_NVR1V61[2] B_NVR1V62[2] B_NVR1V63[2] B_NVR2V13[2] B_NVR2V50[2] B_NVR3V4[2] B_NVR3V8[2] B_NVR3V20[2] B_NVR3V27[2] B_NVR3V36[2] B_NVR3V43[2] B_NVR3V55[2] B_NVR3V59[2] m D1 0 B_NVR1V0[1] B_NVR1V1[1] B_NVR1V2[1] B_NVR1V61[1] B_NVR1V62[1] B_NVR1V63[1] B_NVR2V13[1] B_NVR2V50[1] B_NVR3V4[1] B_NVR3V8[1] B_NVR3V20[1] B_NVR3V27[1] B_NVR3V36[1] B_NVR3V43[1] B_NVR3V55[1] B_NVR3V59[1] D0 1 B_NVR1V0[0] B_NVR1V1[0] B_NVR1V2[0] B_NVR1V61[0] B_NVR1V62[0] B_NVR1V63[0] B_NVR2V13[0] B_NVR2V50[0] B_NVR3V4[0] B_NVR3V8[0] B_NVR3V20[0] B_NVR3V27[0] B_NVR3V36[0] B_NVR3V43[0] B_NVR3V55[0] B_NVR3V59[0] (Hex) Function w - B_NVR1V1[5] B_NVR1V2[5] w B_NVR1V61[5] B_NVR1V62[5] w .m B_NVR1V0[4] B_NVR1V1[4] B_NVR1V2[4] B_NVR1V61[4] B_NVR1V62[4] B_NVR1V63[4] B_NVR2V13[4] B_NVR2V50[4] - GAMCTRN1 1 1 1 1 1 1 1 1 1 B- Gamma (E5h) adjustment "-": Don't care, can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 22 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2. System Command Description 6.2.1. NOP (00h) 00H Inst / Para NOP D/CX 0 WRX RDX 1 D17-8 D7 0 NOP (No Operation) D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 (Code) (00H) - Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command is empty command. It does not have effect on the display module. Description Restriction -However it can be used to terminate RAM data write or read as described in RAMWR (Memory Write), RAMHD (Memory Read) and parameter write commands. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability .m bt 23 Default Status Power On Sequence S/W Reset H/W Reset Flow Chart (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w re nd .co m Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.2. SWRESET (01h): Software Reset 01H Inst / Para SWRESET D/CX 0 WRX RDX 1 D17-8 D7 0 SWRESET (Software Reset) D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 (Code) (01H) - Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter Description -When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values and all source & gate outputs are set to VSS (display off). (See default tables in each command description) Note: The Frame Memory contents are not affected by this command. -It will be necessary to wait 5msec before sending new command following software reset. Restriction -Software Reset command cannot be sent during Sleep Out sequence. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default SWRESET (01H) w w Status Power On Sequence S/W Reset H/W Reset .m bt re Register Availability w nd .co -If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out command. m -The display module loads all display supplier's factory default values to the registers during 5msec. Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A Legend Command Display whole blank screen Flow Chart Parameter Display Set Commands to S/W Default Value Action Mode Sequential transfer Sleep In Mode (c) ORISE Technology Co., Ltd. Proprietary & Confidential 24 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.3. RDDID (04H): Read Display ID 04H Inst / Para RDDID 1 Parameter 2 Parameter 3 Parameter 4 Parameter th rd nd st RDDID (Read Display ID) D/CX 0 1 1 1 1 WRX 1 1 1 1 RDX 1 D17-8 D7 0 ID17 ID27 ID37 D6 0 ID16 ID26 ID36 D5 0 ID15 ID25 ID35 D4 0 ID14 ID24 ID34 D3 0 ID13 ID23 ID33 D2 1 ID12 ID22 ID32 D1 0 ID11 ID21 ID31 D0 0 ID10 ID20 ID30 (Code) (04H) 38h 80h 62h NOTE: "-" Don't care, can be set to VDDI or DGND level -This read byte returns 18-bits display identification information. -The 2 parameter (ID17 to ID10): LCD module's manufacturer ID. -The 3 parameter (ID27 to ID20): LCD module/driver version ID th rd nd Restriction -The 4 parameter (ID37 to UD30): LCD module/driver ID. NOTE: Commands RDID1/2/3 (DAH, DBH, DCH) read data correspond to the parameters 2,3,4 of the command 04H, respectively. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes w .m bt ID1 38h 80h 62h Register Availability re Status Default nd .co Description Serial I/F Mode RDDID (04H) w Power On Sequence S/W Reset H/W Reset Default Value ID2 38h 80h 62h m ID3 38h 80h 62h -The 1 parameter is dummy data st w Parallel I/F M RDDID (04H) Host Driver Legend Command Dummy Clock Flow Chart Dummy Read Parameter Display Send ID1[7:0] Send ID1[7:0] Action Mode Send ID2[7:0] Send ID2[7:0] Sequential transfer Send ID3[7:0] Send ID3[7:0] (c) ORISE Technology Co., Ltd. Proprietary & Confidential 25 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.4. RDDST (09H): Read Display Status 09H Inst / Para RDDST 1 Parameter 2 Parameter 3 Parameter 4 Parameter th rd nd st RDDST (Read Display Status) D/CX 0 1 1 1 WRX 1 1 1 RDX 1 D17-8 D7 0 BSTON ST23 D6 0 MY PF2 D5 0 MX PF1 D4 0 MV PF0 D3 1 ML D2 0 RGB D1 0 ST25 D0 1 (Code) (09H) 00h 61h 00h 00h 1 1 VSSON ST14 INVON ST12 th 5 Parameter 1 1 GCS1 GCS0 TELOM HSON NOTE: "-" Don't care, can be set to VDDI or DGND level Bit BSTON MY MX MV ML RGB ST25 ST24 ST23 PF2 PF1 PF0 IDMON PTLON SLPOUT NORON VSSON ST14 INVON ST12 ST11 DISON TEON GCSEL2 GCSEL1 GCSEL0 TELOM HSON VSON PCLKON DEON ST0 Tearing effect line mode Horizontal Sync. (HS) Vertical Sync, (VS, RGB I/F) Pixel Clock (PCLK, RGB I/F) Data Enable (DE, RGB I/F) For Future Use Description Booster Voltage Status Row Address Order (MY) Column Address Order (MX) Row/Column Exchange (MV) Vertical Refresh Order (ML) RGB/ BGR Order (RGB) For Future Use For Future Use For Future Use ST24 NORO IDMON PTLON SLOUT N ST11 DISON TEON GCS2 VSON PCKON DEON ST0 This command indicates the current status of the display as described in the table below: Value `1' =Booster on, `0' =Booster off `1' =Decrement, (Bottom to Top, when MADCTL (36H) D7='1') `0' =Increment, (Top to Bottom, when MADCTL (36H) D7='0') `1' =Decrement, (Right to Left, when MADCTL (36H) D6='1') `0' =Increment, (Left to Right, when MADCTL (36H) D6='0') `1' = Row/column exchange, (when MADCTL (36H) D5='1') `0' = Normal, (when MADCTL (36H) D5='0') `1' =Decrement, (LCD refresh Bottom to Top, when MADCTL (36H) D4='1') "0"=Increment, (LCD refresh Top to Bottom, when MADCTL (36H) D4='0') `1' =BGR, (When MADCTL (36H) D3='1') `0' =RGB, (When MADCTL (36H) D3='0') `0' `0' `0' "011" = 12-bits / pixel, "101" = 16-bits / pixel, "110" = 18-bits / pixel, others are no define `1' = On, "0" = Off `1' = On, "0" = Off `1' = Out, "0" = In `1' = Normal Display, `0' = Partial Display `1' = Scroll on,"0" = Scroll off `0' `1' = On, "0" = Off `0' `0' `1' = On, "0" = Off `1' = On, "0" = Off "000" = GC0 "001" = GC1 "010" = GC2 "011" = GC3, "100" to "111" = Not defined `0' = mode1, `1' = mode2 `1' = On, `0' = Off `1' = On, `0' = Off `1' = On, `0' = Off `1' = On, `0' = Off `0' Color Pixel Format Definition Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Vertical Scrolling Status For Future Use Inversion Status For Future Use For Future Use Display On/Off Tearing effect line on/off Gamma Curve Selection Description Note: ST0, ST11-ST12, ST14, ST23, ST24 are set to `0' (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 26 re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset ST[31-24] 0000-0000 0xxx-xx00 0000-0000 Default Value (ST31 to ST0) ST[23-16] ST[15-8] ST[7-0] 0110-0001 0000-0000 0000-0000 0xxx-0001 0000-0000 0000-0000 0110-0001 0000-0000 0000-0000 RDDST (09H) RDDST (09H) nd .co Host Driver Serial I/F Mode Parallel I/F Mode m Legend Command bt re Dummy Clock Dummy Read .m Flow Chart Send ST[31:24] Send ST[31:24] Parameter Display w Send ST[23:16] Send ST[23:16] Action Mode Send ST[15:8] w Send ST[15:8] Send ST[7:0] w Sequential transfer Send ST[7:0] (c) ORISE Technology Co., Ltd. Proprietary & Confidential 27 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.5. RDDPM (0AH): Read Display Power Mode 0AH Inst / Para RDDPM 1 Parameter st RDDPM (Read Display Power Mode) D/CX 0 1 WRX 1 RDX 1 D17-8 D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 1 D1 D0 0 D0 (Code) (0AH) 08h- SLPOU NORO nd 2 Parameter 1 1 BSTON IDMON PTLON DISON T N NOTE: "-" Don't care, can be set to VDDI or DGND level Description w Default Status Power On Sequence S/W Reset H/W Reset w Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m Restriction bt -This command indicates the current status of the display as described in the table below: Bit Description Value "1"=Booster on, BSTON Booster Voltage Status "0"=Booster off "1" = Idle Mode On, IDMON Idle Mode On/Off "0" = Idle Mode Off "1" = Partial Mode On, PTLON Partial Mode On/Off "0" = Partial Mode Off "1" = Sleep Out, SLPON Sleep In/Out "0" = Sleep In "1" = Normal Display, NORON Display Normal Mode On/Off "0" = Partial Display "1" = Display On, DISON Display On/Off "0" = Display Off D1 Not Used "0" D0 Not Used "0" re - w nd .co Host Driver Default Value (D7 to D0) 0000_1000 (08h) 0000_1000 (08h) 0000_1000 (08h) m Availability Yes Yes Yes Yes Yes Legend Serial I/F Mode RDDPM (0AH) Parallel I/F Mode RDDPM (0AH) Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 28 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.6. RDDMADCTR (0BH): Read Display MADCTR 0BH Inst / Para RDDMADCTR 1 Parameter nd st RDDMADCTR (Read Display MADCTR) D/CX 0 1 WRX 1 RDX 1 D17-8 D7 0 D6 0 MY D5 0 MV D4 0 ML D3 1 RGB D2 0 D2 D1 1 D1 D0 1 D0 (Code) (0BH) 00h MX 2 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level Description Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In bt re Status Power On Sequence S/W Reset H/W Reset w w .m Register Availability Default w nd .co Host Driver -This command indicates the current status of the display as described in the table below: Bit Description Value MX Row Address Order `1' =Decrement, "0"=Increment MY Column Address Order `1' =Decrement, "0"=Increment `1' = Row/column exchange (MV=1) MV Row/Column Order (MV) `0' = Normal (MV=0) `1' =LCD Refresh Top to Bottom ML Vertical Refresh Order `0' =LCD Refresh Bottom to Top RGB RGB/BGR Order `1' =BGR, "0"=RGB D2 Not Used `0' D1 Not Used `0' D0 Not Used `0' Default Value (D7 to D0) 0000_0000 (00h) No change 0000_0000 (00h) m Availability Yes Yes Yes Yes Yes Serial I/F Mode RDDMADCTR (0BH) Parallel I/F Mode RDDMADCTR (0BH) Legend Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 29 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.7. RDDCOLMOD (0CH): Read Display Pixel Format 0CH Inst / Para RDDCOLMOD 1 Parameter nd st RDDCOLMOD (Read Display Pixel Format) D/CX 0 1 WRX 1 RDX 1 D17-8 D7 0 D6 0 VIPF2 D5 0 VIPF1 D4 0 VIPF0 D3 1 D3 D2 1 IFPF2 D1 0 IFPF1 D0 0 IFPF0 (Code) (0CH) 66h 2 Parameter 1 1 VIPF3 NOTE: "-" Don't care, can be set to VDDI or DGND level Restriction w w Status w Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In bt re Availability Yes Yes Yes Yes Yes Default Value IFPF[2:0] VIPF[3:0] 0101 (16-bits/pixel) 0110 (18-bits/pixel) No Change No Change 0101 (16-bits/pixel) 0110 (18-bits/pixel) VIPF[3:0] 0101 5 0110 6 0111 7 1110 14 Others are no define and invalid RGB Interface Color Format 16-bits/pixel (1-times data transfer) 18-bits/pixel (1-times data transfer) Reserved 18-bits/pixel (3-times data transfer) Default Power On Sequence S/W Reset H/W Reset .m nd .co Host Driver Description m -This command indicates the current status of the display as described in the table below: IFPF[2:0] MCU Interface Color Format 011 3 12-bits/pixel 101 5 16-bits/pixel 110 6 18-bits/pixel 111 7 Reserved Others are no define and invalid Serial I/F Mode RDDCOLMOD (0CH) Parallel I/F Mode RDDCOLMOD (0CH) Legend Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 30 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.8. RDDIM (0DH): Read Display Image Mode 0DH Inst / Para RDDIM 1 Parameter nd st RDDIM (Read Display Image Mode D/CX 0 1 WRX 1 RDX 1 D17-8 D7 0 D6 0 D6 D5 0 INVON D4 0 D4 D3 1 D3 D2 1 GCS2 D1 0 GCS1 D0 1 GCS0 (Code) (0DH) 00h 2 Parameter 1 1 VSSON NOTE: "-" Don't care, can be set to VDDI or DGND level Restriction Register Availability Default Status Power On Sequence S/W Reset H/W Reset w w Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In bt re Availability Yes Yes Yes Yes Yes .m w nd .co Host Driver Description -This command indicates the current status of the display as described in the table below: Bit Description Value "1" = Vertical scrolling is On, VSSON Vertical Scrolling On/Off "0" = Vertical scrolling is Off D6 For Future Use "0" (Not used) "1" = Inversion is On, INVON Inversion On/Off "0" = Inversion is Off D4 For Future Use "0" (Not used) D3 For Future Use "0" (Not used) GCS2 "000" = GC0, "001" = GC1, GCS1 Gamma Curve Selection "010" = GC2, GCS0 "011" = GC3, "100" to "111" = Not defined Default Value (D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h) m Serial I/F Mode RDDIM (0DH) Parallel I/F Mode RDDIM (0DH) Legend Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 31 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.9. RDDSM (0EH): Read Display Signal Mode 0EH Inst / Para RDDSM 1 Parameter nd st RDDSM (Read Display Signal Mode) D/CX 0 1 WRX 1 RDX 1 D17-8 D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D1 D0 0 D0 (Code) (0EH) 00h 2 Parameter 1 1 TEON TELOM HSON NOTE: "-" Don't care, can be set to VDDI or DGND level VSON PCKON DEON -This command indicates the current status of the display as described in the table below: Bit TEON TELOM Description HSON VSON PCKON DEON D1 D0 Description Tearing Effect Line On/Off Tearing effect line mode Horizontal Sync. (RGB I/F) On/Off Vertical Sync. (RGB I/F) On/Off Pixel Clock (PCLK, RGB I/F) On/Off Data Enable (DE, RGB I/F) On/Off Not Used Not Used Value "1" = On, "0" = Off "0" = mode1, "1" = mode2 "1" = On, "0" = Off "1" = On, "0" = Off "1" = On, "0" = Off "1" = On, "0" = Off "1" = On, "0" = Off "1" = On, "0" = Off Default Status Power On Sequence S/W Reset H/W Reset w w .m Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In re Restriction bt w nd .co Availability Yes Yes Yes Yes Yes Default Value (D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h) m Legend Command Serial I/F Mode RDDSM (0EH) Parallel I/F Mode RDDSM (0EH) Host Driver Flow Chart Send D[7:0] Dummy Read Parameter Display Action Mode Send D[7:0] Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 32 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.10. RDDSDR (0FH): Read Display Self-Diagnostic Result 0FH Inst / Para RDDSDR 1 Parameter nd st RDDSDR (Read Display Self-Diagnostic Result) D/CX 0 1 WRX 1 RDX 1 D17-8 D7 0 D6 0 FUND D5 0 ATTD D4 0 BRD D3 1 D3 D2 1 D2 D1 1 D1 D0 1 D0 (Code) (0FH) 00h 2 Parameter 1 1 RELD NOTE: "-" Don't care, can be set to VDDI or DGND level -This command indicates the current status of the display as described in the table below: Bit RELD FUND ATTD BRD D3 D2 D1 D0 Description Register Loading Detection Functionality Detection Chip Attachment Detection Display Glass Break Detection Not Used Not Used Not Used Not Used Value See section 6.15.1 See section 6.15.1 See section 6.15.3 See section 6.15.4 "0" "0" "0" "0" Description Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In re Default w Status Power On Sequence S/W Reset H/W Reset w .m Register Availability bt w nd .co Host Driver 33 Default Value (D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h) m Availability Yes Yes Yes Yes Yes Serial I/F Mode RDDSDR (0FH) Parallel I/F Mode RDDSTR (0FH) Legend Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.11. SLPIN (10H): Sleep In 10H Inst / Para SLPIN st SLPIN (Sleep In) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 (Code) (10H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No parameter -This command causes the LCD module to enter the minimum power consumption mode. -In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped. Sleep In VDDI 1.6V-3.6V m nd .co re 34 0V 0V Blanking display (over 1frame display) * VDD Gate Output Source Output VCOM Output Description Internal counter Internal Oscillator DC charge in capacitors VGH VGL AVDD 2.6V-3.5V STOP 0V STOP STOP bt DISCHARGE 0V or VDD 0V or VDD 0V 0V or VDD 0V IC Internal reset * Note: complete 1 frame display (ex: continue 2-falling edges of VS) -MCU interface and memory are still working and the memory keeps its contents -This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out Command (11H). Restriction -It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. -It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w w .m Availability Yes Yes Yes Yes Yes Default Value Sleep In mode Sleep In mode Sleep In mode Default Status Power On Sequence S/W Reset H/W Reset (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B -It takes about 120msec to get into Sleep In mode (booster off state) after SLPIN command issued. -The results of booster off can be check by RDDST (09H) command Bit31. SPLIN (10H) Legend Stop DC/DC Converte Stop Internal Oscillator Command Flow Chart Display whole blank screen (Automatic No effect to DISP ON/OFF Command) Parameter Display Action Mode Drain charge from LCD panel (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt re 35 nd .co m Sleep In Sequential transfer Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.12. SLPOUT (11H): Sleep Out 11H Inst / Para SLPOUT st SLPOUT (Sleep Out) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 (Code) (11H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command turns off sleep mode. -In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started. Sleep Out VDDI 1.6V-3.6V m STOP 0V or VDD 0V 0V or VDD STOP 0V VDD Internal Oscillator AVDD VGL Description VGH Internal counter IC Internal reset Gate Output Source Output VCOM Output Start 2.6V-3.5V re STOP 0V 0V nd .co Start Memory Contents Memory Contents w w Blanking display (over 1frame display) * .m STOP 0V 0V bt If DISPON 29H is set Availability Yes Yes Yes Yes Yes Default Value Sleep In mode Sleep In mode Sleep In mode 36 * Note: complete 1 frame display (ex: continue 2-falling edges of VS) -This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10H). -It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. Restriction -DRIVER loads all default values of extended and test command to the registers during this 5msec and there cannot be any abnormal visual effect on the display image if those default and register values are same when this load is done and when the DRIVER is already Sleep Out mode. -DRIVER is doing self-diagnostic functions during this 5msec. See also section 8.19. -It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default (c) ORISE Technology Co., Ltd. Proprietary & Confidential w Status Power On Sequence S/W Reset H/W Reset Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B -It takes 120msec to become Sleep Out mode (booster on mode) after SLPOUT command issued. -The results of booster on can be checked by RDDST (09H) command Bit31. SLPOUT (11H) Start Internal Oscillator Start DC-DC Converter Charge Offset voltage for LCD Panel Display whole blank screen for 2 frames (Automatic No effect to DISP ON/OFF Display Memory contents in accordance with the current command Legend Command Parameter Display Flow Chart Action Mode Sequential transfer Sleep Out (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 37 bt re nd .co m table settings Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.13. PTLON (12H): Partial Display Mode On 12H Inst / Para PTLON st PTLON (Partial Display Mode On) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 (Code) (12H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command turns on Partial mode. The partial mode window is described by the Partial Area command (30H) Description Restriction -To leave Partial mode, the Normal Display Mode On command (13H) should be written. -There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On. This command has no effect when Partial mode is active. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 38 Flow Chart See Partial Area (30H) bt Status Power On Sequence S/W Reset H/W Reset re nd .co Register Availability Default Value Normal Mode On Normal Mode On Normal Mode On m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.14. NORON (13H): Normal Display Mode On 13H Inst / Para NORON st NORON (Normal Display Mode On) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 1 (Code) (13H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command returns the display to normal mode. Description -Normal display mode on means Partial mode off, Scroll mode Off. -Exit from NORON by the Partial mode On command (12H) -There is no abnormal visual effect during mode change from Normal mode On to Partial mode On. Restriction -This command has no effect when Normal Display mode is active. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability Flow Chart -See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 39 Default Status Power On Sequence S/W Reset H/W Reset re nd .co Default Value Normal Mode On Normal Mode On Normal Mode On m Availability Yes Yes Yes Yes Yes Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.15. INVOFF (20H): Display Inversion Off 20H Inst / Para INVOFF st INVOFF (Display Inversion Off) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 (Code) (20H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command is used to recover from display inversion mode. -This command makes no change of contents of frame memory. -This command does not change any other status. Top-Left (0,0) Description Memory Display Restriction -This command has no effect when module is already inversion off mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m bt re Default Status Power On Sequence S/W Reset H/W Reset w w w Register Availability nd .co Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off m Legend Command (Example) Display Inversion On Mode Parameter Display Flow Chart INVOFF (20H) Action Mode Sequential transfer Display Inversion OFF Mode (c) ORISE Technology Co., Ltd. Proprietary & Confidential 40 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.16. INVON (21H): Display Inversion On 21H Inst / Para INVON st INVON (Display Inversion On) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 (Code) (21H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command is used to enter into display inversion mode -This command makes no change of contents of frame memory. -This command does not change any other status. -To exit from Display Inversion On, the Display Inversion Off command (20H) should be written. Memory Restriction -This command has no effect when module is already Inversion On mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m bt re Register Availability Default Status Power On Sequence S/W Reset H/W Reset w w w nd .co Display Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off Description Top-Left (0,0) (Example) m Legend Command Display Inversion OFF Mode Parameter Display Flow Chart INVON (21H) Action Mode Sequential transfer Display Inversion ON Mode (c) ORISE Technology Co., Ltd. Proprietary & Confidential 41 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.17. GAMSET (26H): Gamma Set 26H Inst / Para GAMSET st GAMSET (Gamma Set) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 GC6 D5 1 GC5 D4 0 GC4 D3 0 GC3 D2 1 GC2 D1 1 GC1 D0 0 GC0 (Code) (26H) 01h 1 Parameter 1 GC7 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curves are defined in section 6.12. The curve is selected by setting the appropriate bit in the parameter as described in the Table. GC [7:0] Description 01h 02h 04h Parameter GC0 GC1 GC2 Curve Selected Gamma Curve 1 (G2.2) Gamma Curve 2 (G1.8) Gamma Curve 3 (G2.5) Gamma Curve 4 (G1.0) Restriction -Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma curve until valid is received. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes w w Default Status Power On Sequence S/W Reset H/W Reset w .m bt Register Availability re nd .co 08h GC3 Note: All other values are undefined. m Default Value 01h 01h 01h ---------------GAMSET (26H) Legend Command Parameter Display Flow Chart 1 Parameter: GC[7:0] st Action Mode Sequential transfer New Gamma Curve Loaded (c) ORISE Technology Co., Ltd. Proprietary & Confidential 42 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.18. DISPOFF (28H): Display Off 28H Inst / Para DISPOFF st DISPOFF (Display Off) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 (Code) (28H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and blank page inserted. -This command makes no change of contents of frame memory. -This command does not change any other status. -There will be no abnormal visible effect on the display. -Exit from this command by Display On (29H) Top-Left (0,0) Memory Display OFF Description VDDI VDD Gate Output Source Output VCOM Output bt re nd .co Display 1.6V-3.6V 2.6V-3.5V STOP 0V STOP Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off (Example) w w .m 0V 0V 43 Blanking display (over 1 frame display) * Internal counter Internal Oscillator VGH VGL AVDD IC Internal reset * Note: complete 1 frame display (ex: continue 2-falling edges of VS) Restriction -This command has no effect when module is already in Display Off mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability Default Status Power On Sequence S/W Reset H/W Reset (c) ORISE Technology Co., Ltd. Proprietary & Confidential w m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Legend Display On Mode Command Parameter DISPOFF (28H) Display Flow Chart Action Mode Sequential transfer Display OFF Mode (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 44 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.19. DISPON (29H): Display On 29H Inst / Para DISPON st DISPON (Display On) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1 (Code) (29H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. -This command makes no change of contents of frame memory. -This command does not change any other status. re nd .co Display ON m 1.6V-3.6V 2.6V-3.5V Memory Contents Memory Contents Top-Left (0,0) (Example) Memory Display VDD Description Gate Output Source Output VCOM Output Internal counter Blanking display (over 1 frame display) * w w .m STOP 0V 0V Start STOP Internal Oscillator VGH VGL AVDD IC Internal reset * Note: complete 1 frame display (ex: continue 2-falling edges of VS) Restriction -This command has no effect when module is already in Display On mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability w Default Status Power On Sequence S/W Reset H/W Reset bt 45 VDDI Default Value Display off Display off Display off (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Legend Display OFF Mode Command Parameter DISPON (29H) Display Flow Chart Action Mode Sequential transfer Display ON Mode (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 46 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.20. CASET (2AH): Column Address Set 2AH Inst / Para CASET 1 Parameter 2 Parameter 3 Parameter th rd nd st CASET (Column Address Set) D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D7 0 XS15 XS7 XE15 D6 0 XS14 XS6 XE14 XE6 D5 1 XS13 XS5 XE13 XE5 D4 0 XS12 XS4 XE12 XE4 D3 1 XS11 XS3 XE11 XE3 D2 0 XS10 XS2 XE10 XE2 D1 1 XS9 XS1 XE9 XE1 D0 0 XS8 XS0 XE8 XE0 (Code) (2AH) 00h 00h 4 Parameter 1 1 XE7 NOTE: "-" Don't care, can be set to VDDI or DGND level -This command is used to define area of frame memory where MCU can access. -This command makes no change on the other driver status. -Each value represents one column line in the Frame Memory. -The value of XS [15:0] and XE [15:0] are referred when RAMWR command comes. (Example) XS[15:0] Description XS [15:0] always must be equal to or less than XE [15:0] 1. 176x220 memory base (GM1, GM0 = "00") (Parameter range: 0 XS [15:0] XE [15:0] 175 (00AFh)): MV="0" If the "XS" or "XE" are large then 175d, it become 175d (Parameter range: 0 XS [15:0] XE [15:0] 219d (00DBh)): MV="1" If the "XS" or "XE" are large then 219d, it become 219d 2. 176x176 memory base (GM1, GM0 = "01") Restriction (Parameter range: 0 XS [15:0] XE [15:0] 175 (00AFh)): MV="0" If the "XS" or "XE" are large then 175d, it become 175d (Parameter range: 0 XS [15:0] XE [15:0] 175 (00AFh)): MV="1" If the "XS" or "XE" are large then 175d, it become 175d 1. 176x132 memory base (GM1, GM0 = "11") (Parameter range: 0 XS [15:0] XE [15:0] 175 (00AFh)): MV="0" If the "XS" or "XE" are large then 175d, it become 175d (Parameter range: 0 XS [15:0] XE [15:0] 131d (0083h)): MV="1" If the "XS" or "XE" are large then 131d, it become 131d Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored. w .m Availability Yes Yes Yes Yes Yes (c) ORISE Technology Co., Ltd. Proprietary & Confidential 47 bt re nd .co XE[15:0] m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. 176x220 memory base (GM1, GM0 = "00") Status Power On Sequence S/W Reset H/W Reset XS [15:0] 0000h Default Value XE [15:0] (MV='0') XE [15:0] (MV='1') 00AFh (175d) 00AFh (175d) 00DBh (219d) 00AFh (175d) Default Value XE [15:0] (MV='0') 2. 176x176 memory base (GM1, GM0 = "01") Status Default Power On Sequence S/W Reset H/W Reset XS [15:0] 0000h XE [15:0] (MV='1') 00AFh (175d) 3. 176x132 memory base (GM1, GM0 = "11") Status Power On Sequence S/W Reset H/W Reset XS [15:0] 0000h Default Value XE [15:0] (MV='0') XE [15:0] (MV='1') 00AFh (175d) 00AFh (175d) 0083h (132d) 00AFh (175d) Partial Mode CASET (2AH) Flow Chart rd w st nd 1 & 2 Parameter: YS[15:0] th w rd th RASET (2BH) w 1st & 2nd Parameter: XS[15:0] .m If Needed bt re nd .co 48 m Legend Command RAMWR (2CH) Parameter Display Image Data D1[B:0],D2[B:0]......Dn[B:0] Action Mode Note: B=17 Any Command Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.21. RASET (2BH): Row Address Set 2BH Inst / Para RASET 1 Parameter 2 Parameter 3 Parameter th rd nd st RASET (Row Address Set) D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D7 0 YS15 YS7 YE15 D6 0 YS14 YS6 YE14 YE6 D5 1 YS13 YS5 YE13 YE5 D4 0 YS12 YS4 YE12 YE4 D3 1 YS11 YS3 YE11 YE3 D2 0 YS10 YS2 YE10 YE2 D1 1 YS9 YS1 YE9 YE1 D0 1 YS8 YS0 YE8 YE0 (Code) (2BH) 00h 00h 4 Parameter 1 1 YE7 NOTE: "-" Don't care, can be set to VDDI or DGND level -This command is used to define area of frame memory where MCU can access. -This command makes no change on the other driver status. -Each value represents one column line in the Frame Memory. -The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes. Description YS[15:0] When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored. (Parameter range: 0 YS [15:0] YE [15:0] 219 (0DBh)): MV="0" If the "XS" or "XE" are large then 219d, it become 219d (Parameter range: 0 YS [15:0] YE [15:0] 175 (00AFh)): MV="1" If the "XS" or "XE" are large then 175d, it become 175d 2. 176x176 memory base (GM1, GM0 = "01") Restriction (Parameter range: 0 YS [15:0] YE [15:0] 175 (00AFh)): MV="0" If the "XS" or "XE" are large then 175d, it become 175d (Parameter range: 0 YS [15:0] YE [15:0] 175 (00AFh)): MV="1" If the "XS" or "XE" are large then 175d, it become 175d 3. 176x132 memory base (GM1, GM0 = "11") (Parameter range: 0 YS [15:0] YE [15:0] 131 (0083h)): MV="0" If the "XS" or "XE" are large then 131d, it become 131d (Parameter range: 0 YS [15:0] YE [15:0] 175 (00AFh)): MV="1" If the "XS" or "XE" are large then 175d, it become 175d Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w 1. 176x220 memory base (GM1, GM0 = "00") w YS [15:0] always must be equal to or less than YE [15:0] .m YE[15:0] bt Availability Yes Yes Yes Yes Yes 49 (c) ORISE Technology Co., Ltd. Proprietary & Confidential re nd .co (Example) m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. 176x220 memory base (GM1, GM0 = "00") Status Power On Sequence S/W Reset H/W Reset YS [15:0] 0000h Default Value YE [15:0] (MV='0') YE [15:0] (MV='1') 0DBh (219d) 0DBh (219d) 00AFh (175d) 0DBh (219d) Default Value YE [15:0] (MV='0') 2. 176x176 memory base (GM1, GM0 = "01") Status Default Power On Sequence S/W Reset H/W Reset YS [15:0] 0000h YE [15:0] (MV='1') 00AFh (175d) 3. 176x132 memory base (GM1, GM0 = "11") Status Power On Sequence S/W Reset H/W Reset YS [15:0] 0000h Default Value YE [15:0] (MV='0') YE [15:0] (MV='1') 0083h (131d) 0083h (131d) 00AFh (175d) 0083h (131d) Partial Mode CASET (2AH) bt re If Needed Flow Chart rd w st nd 1 & 2 Parameter: YS[15:0] th w rd th RASET (2BH) w st nd 1 & 2 Parameter: XS[15:0] .m nd .co If Needed 50 m Legend RAMWR (2CH) Command Parameter Image Data D1[B:0],D2[B:0]......Dn[B:0] Display Action Mode Any Command Note: B=17 Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.22. RAMWR (2CH): Memory Write 2CH Inst / Para RAMWR 1 Parameter th st RAMWR (Memory Write) D/CX 0 1 1 WRX RDX 1 1 1 D17-8 D17-8 D7 0 D7 D6 0 D6 D6 D5 1 D5 D5 D4 0 D4 D4 D3 1 D3 D3 D2 1 D2 D2 D1 0 D1 D1 D0 0 D0 D0 (Code) (2CH) - N Parameter 1 1 D17-8 D7 NOTE: "-" Don't care, can be set to VDDI or DGND level -This command is used to transfer data from MCU to frame memory. -This command makes no change to the other driver status. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. -The Start Column/Start Row positions are different in accordance with MADCTR setting. (See section 6.6) -Then D[B:0] is stored in frame memory and the column register and the row register incremented as section 6.5.2. -Sending any other command can stop Frame Write. Description In all color modes, there is no restriction on length of parameters. 1. 176x220 memory base (GM1, GM0 = "00") 176x220x18-bits memory can be written by this command Memory range: (0000h,0000h) -> (00AFh, 00DBh) Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w 3. 176x132 memory base (GM1, GM0 = "11") 176x220x18-bits memory can be written by this command Memory range: (0000h,0000h) -> (00AFh, 0083h) w .m Restriction 2. 176x176 memory base (GM1, GM0 = "01") 176x220x18-bits memory can be written by this command Memory range: (0000h,0000h) -> (00AFh, 00AFh) bt 51 re Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared Default Status Power On Sequence S/W Reset H/W Reset (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Legend RAMWR (2CH) Command Parameter Flow Chart Image Data D1[B:0],D2[B:0]......Dn[B:0] Display Action Mode Any Command Sequential transfer Note: B=17 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 52 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.23. RGBSET (2DH): Colour Setting 2DH Inst / Para RGBSET 1 Parameter nd st RGBSET (Colour Setting) D/CX 0 1 1 1 1 1 1 1 1 WRX RDX 1 1 1 1 1 1 1 1 1 D17-8 D7 0 R007 : Raa7 G007 : Gbb7 B007 : D6 0 R006 : Raa6 G006 : Gbb6 B006 : Bcc6 D5 1 R005 : Raa5 005 : Gbb5 B005 : Bcc5 D4 0 R004 : Raa4 G004 : Gbb4 B004 : Bcc4 D3 1 R003 : Raa3 G003 : Gbb3 B003 : Bcc3 D2 1 R002 : Raa2 G002 : Gbb2 B002 : Bcc2 D1 0 R001 : Raa1 G001 : Gbb1 B001 : Bcc1 D0 1 R000 : Raa0 G000 : Gbb0 B000 : Bcc0 (Code) (2DH) - -This command is used to define the LUT for 12-bits-to-18-bits / 16bits-to-18-bits colors depth conversations. -262K-colors used. -LUT has total trough 128 parameters. -In this condition, 4K-color (4-4-4) and 65K-color(5-6-5) data input are transferred 6(R)-6(G)-6(B) through RGB LUT table. (aa=31, bb=63, cc=31) -This command has no effect on other commands/parameters and Contents of frame memory. Restriction Do not send any command before the last data is sent or LUT is not defined correctly. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Description .m bt -Visible change takes effect next time the Frame Memory is written . re Default Status Power On Sequence S/W Reset H/W Reset w w Register Availability w nd .co Default Value LUT default value Contents of the look-up table protected LUT default value m Availability Yes Yes Yes Yes Yes n Parameter 1 1 Bcc7 NOTE: "-" Don't care, can be set to VDDI or DGND level Legend RGBSET (2DH) Command Parameter 1 Parameter: Flow Chart th st Display n arameter: Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 53 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.24. RAMHD (2EH): Memory Read 2EH Inst / Para RAMHD 1 Parameter 2 Parameter th nd st RAMHD (Memory Read) D/CX 0 1 1 1 WRX 1 1 1 RDX 1 D17-8 D17-8 D7 0 D7 D6 0 D6 D6 D5 1 D5 D5 D4 0 D4 D4 D3 1 D3 D3 D2 1 D2 D2 D1 1 D1 D1 D0 0 D0 D0 (Code) (2EH) - (N+1) Parameter 1 1 D17-8 D7 NOTE: "-" Don't care, can be set to VDDI or DGND level -This command is used to transfer data from frame memory to MCU. -This command makes no change to the other driver status. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. Description -Then D[B:0] is read back from the frame memory and the column register and the row register incremented as section 6.5.2. -Frame Read can be canceled by sending any other command. -See section 6.4 "Data color coding" for color coding (18-bits cases), when there is used 12, 16, and 18-bits data lines for image data. -Memory read is only possible via the SPI and parallel interface. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m bt Restriction -In all color modes, the Frame Read is always 18-bits and there is no restriction on length of parameters. re w Default Status Power On Sequence S/W Reset H/W Reset w w Register Availability Note: B=17 RAMRD (2EH) Legend Dummy Read Flow Chart Command nd .co -The Start Column/Start Row positions are different in accordance with MADCTR setting. (See section 6.7) Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared m Availability Yes Yes Yes Yes Yes Parameter Display Image Data D1[B:0],D2[B:0]......Dn[B:0] Action Mode Sequential transfer Any Command (c) ORISE Technology Co., Ltd. Proprietary & Confidential 54 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.25. PTLAR (30H): Partial Area 30H Inst / Para PTLAR 1 Parameter 2 Parameter 3 Parameter th rd nd st PTLAR (Partial Area) D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D7 0 PSL15 PSL7 PEL15 D6 0 PSL14 PSL6 PEL14 PEL6 D5 1 PSL13 PSL5 PEL13 PEL5 D4 1 PSL12 PSL4 PEL12 PEL4 D3 0 PSL11 PSL3 PEL11 PEL3 D2 0 PSL10 PSL2 PEL10 PEL2 D1 0 PSL9 PSL1 PEL9 PEL1 D0 0 PSL8 PSL0 PEL8 PEL0 (Code) (30H) 00h 00h 4 Parameter 1 1 PEL7 NOTE: "-" Don't care, can be set to VDDI or DGND level -This command defines the partial mode's display area. -There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter. Start Row PSL [15:0] Non-displaying Area PEL [15:0] End Row Non-displaying Area -If End Row > Start Row, when MADCTL ML='1' End Row w w Description w PEL [15:0] .m bt 55 Non-displaying Area Partial Display Area PSL [15:0] Start Row Non-displaying Area -If End Row < Start Row, when MADCTL ML='0' End Row PEL [15:0] Non-displaying Area PSL [15:0] Start Row Partial Display Area Partial Display Area -If End Row = Start Row then the Partial Area will be one row deep. (c) ORISE Technology Co., Ltd. Proprietary & Confidential re nd .co -If End Row > Start Row, when MADCTL ML='0' Partial Display Area m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B -PEL [15:0] always must be equal to or less than PSL [15:0] -When PEL [15:0] or PSL [15:0] are greater than maximum row address like below, data of out of range will be ignored. 1. 176x220 memory base (GM1, GM0 = "00") (Parameter range: 0 PSL [15:0] PEL [15:0] 219 (0DBh)) If the "PSL" or "PEL" are large then 219d, it become 219d Restriction 2. 176x176 memory base (GM1, GM0 = "01") (Parameter range: 0 PSL [15:0] PEL [15:0] 176 (00AFh)) If the "PSL" or "PEL" are large then 176d, it become 176d 3. 176x132 memory base (GM1, GM0 = "11") (Parameter range: 0 PSL [15:0] PEL [15:0] 131 (0083h)) If the "PSL" or "PEL" are large then 131d, it become 131d 1. 176x220 memory base (GM1, GM0 = "00") Status Power On Sequence S/W Reset H/W Reset re bt 56 nd .co PSL [15:0] 0000h PSL [15:0] 0000h PSL [15:0] 0000h Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes m Default Value PEL [15:0] 00DBh 2. 176x176 memory base (GM1, GM0 = "01") Status Default .m Default Value PEL [15:0] 00AFh w 3. 176x132 memory base (GM1, GM0 = "11") Status Default Value PEL [15:0] 0083h Power On Sequence S/W Reset H/W Reset (c) ORISE Technology Co., Ltd. Proprietary & Confidential w Power On Sequence S/W Reset H/W Reset w Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. To Enter Partial Mode PTLAR (30H) 1 & 2 Parameter: PSL[15:0] 3 & 4 Parameter: PEL[15:0] Flow Chart rd th st nd 2. To Exit Partial Mode Partial Mode DISPOFF (28H) NORON (13H) Partial Mode OFF Optional to prevent tearing effect image display Legend Command PTLON (12H) RAMRW (2CH) Partial Mode Parameter m Display nd .co DISON (29H) Image Data D1[B:0],D2[B:0]... ...Dn[B:0] Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w 57 w w .m bt re Note: B=17 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.26. SCRLAR (33H): Scroll Area 33H Inst / Para SCRLAR 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter th th th rd nd st SCRLAR (Scroll Area) D/CX 0 1 1 1 1 1 WRX RDX 1 1 1 1 1 1 D17-8 D7 0 TFA15 TFA7 VSA7 BFA15 D6 0 TFA14 TFA6 VSA6 BFA14 BFA6 D5 1 TFA13 TFA5 VSA5 BFA13 BFA5 D4 1 TFA12 TFA4 VSA4 BFA12 BFA4 D3 0 TFA11 TFA3 VSA3 BFA11 BFA3 D2 0 TFA10 TFA2 VSA2 BFA10 BFA2 D1 1 TFA9 TFA1 VSA9 VSA1 BFA9 BFA1 D0 1 TFA8 TFA0 VSA8 VSA0 BFA8 BFA0 00h 00h (Code) (33H) 00h 00h VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 6 Parameter 1 1 BFA7 NOTE: "-" Don't care, can be set to VDDI or DGND level -When MADCTR ML=0 st nd Top-Left (0,0) Top Fixed Area TFA [15:0] .m 58 bt The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory row address. th th re Scroll Fixed Area Description -When MADCTR ML=1 The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). rd th The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the top most line of the Top Fixed Area. The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory and Display). Top-Left (0,0) th th st nd w w VSFA [15:0] Bottom Fixed Area BFA [15:0] Bottom Fixed Area BFA [15:0] Scroll Fixed Area VSFA [15:0] Top Fixed Area TFA [15:0] First line read from frame memory -See Section 6.5.4 for details of the Memory to Display Mapping. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w nd .co The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). rd th The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the Top Fixed Area. m -This command defines the Vertical Scrolling Area of the display. First line read from frame memory Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. 176x220 memory base (GM1, GM0 = "00") -The condition is 0 (TFA+VSA+BFA) 220, otherwise Scrolling mode is undefined. 2. 176x176 memory base (GM1, GM0 = "01") Restriction -The condition is 0 (TFA+VSA+BFA) 176, otherwise Scrolling mode is undefined. 3. 176x132 memory base (GM1, GM0 = "11") -The condition is 0 (TFA+VSA+BFA) 132, otherwise Scrolling mode is undefined. -In Vertical Scroll Mode, MADCTR parameter MV should be set to `0'-this only affects the Frame Memory Write. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In 1. 176x220 memory base (GM1, GM0 = "00") Status Power On Sequence S/W Reset H/W Reset 2. 176x176 memory base (GM1, GM0 = "01") Status Default Power On Sequence S/W Reset H/W Reset TFA [15:0] 0000h Availability Yes Yes Yes Yes Yes Register Availability nd .co re TFA [15:0] 0000h TFA [15:0] 0000h 59 m Default Value VSA [15:0] 00DCh BFA [15:0] 0000h Default Value VSA [15:0] 00B0h BFA [15:0] 0000h 3. 176x132 memory base (GM1, GM0 = "11") .m bt w Status Default Value VSA [15:0] 0084h BFA [15:0] 0000h (c) ORISE Technology Co., Ltd. Proprietary & Confidential w Power On Sequence S/W Reset H/W Reset w Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. To Enter Vertical Scroll Mode Normal Mode SCRLAR (33H) 1st & 2nd Parameter: TFA[15:0] 3rd & 4th Parameter VSA[15:0] 5th & 6th Parameter BFA[15:0] Legend Command Parameter Display Action Mode Sequential transfer nd .co 1st & 2nd Parameter XS[15:0] 3rd & 4th Parameter XE[15:0] RASET (2BH) m Redefines the Frame Memory Window that the scroll data will be written to. See NOTE Optional - It may be necessary to redefine the Frame Memory Write Direction. Apr. 25, 2006 Preliminary Version: 0.1 CASET (2AH) 1st & 2nd Parameter YS[15:0] 3rd & 4th Parameter YE[15:0] w w (c) ORISE Technology Co., Ltd. Proprietary & Confidential w .m Parameter: MY,MX,MV,ML,RGB RAMRW (2CH) Scroll Image Data VSCSAD (37H) 1st & 2nd Parameter SSA[15:0] Scroll Mode NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed. bt 60 Flow Chart Only required for non-rolling scrolling MADCTR (36H) re Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 2. Continuous Scroll Normal Mode CASET (2AH) 1 st Legend Command Parameter Display &2 nd Parameter XS[15:0] Action Mode Sequential transfer 3rd & 4th Parameter XE[15:0] RASET (2BH) RAMRW (2CH) Only required for non-rolling scrolling Scroll Image Data Flow Chart w w w .m 1st & 2nd Parameter SSA[15:0] 3. To Exit Vertical Scroll Mode Scroll Mode DISOFF (28H) NORON (13H) / PTLON (12H) Scroll Mode OFF RAMRW (2CH) Image Data D1[B:0],D2[B:0]... ...Dn[B:0] DISON (29H) OptionTo prevent Tearing Effect Image Display Note: B=17 Note: Scroll Mode can be exit by both the Normal Display Mode On (13H) and Partial Mode On (12H) commands. (c) ORISE Technology Co., Ltd. Proprietary & Confidential bt 61 VSCSAD (37H) re nd .co 3rd & 4th Parameter YE[15:0] m Apr. 25, 2006 Preliminary Version: 0.1 1st & 2nd Parameter YS[15:0] Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.27. TEOFF (34H): Tearing Effect Line OFF 34H Inst / Para TEOFF st TEOFF (Tearing Effect Line OFF) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 (Code) (34H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. -This command has no effect when Tearing Effect output is already OFF. Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Default Value RCM1, RCM0 = "00", "1x" RCM1, RCM0 = "01" ON .m bt m Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Legend Command TE Line Output ON w w Parameter Display Flow Chart w TEOFF (34H) Action Mode Sequential transfer TE Line Output OFF (c) ORISE Technology Co., Ltd. Proprietary & Confidential 62 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.28. TEON (35H): Tearing Effect Line ON 35H Inst / Para TEON st TEON (Tearing Effect Line ON) D/CX 0 WRX RDX 1 D17-8 D7 0 0 D6 0 0 D5 1 0 D4 1 0 D3 0 0 D2 1 0 D1 0 0 D0 1 TELOM (Code) (35H) 00h 1 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -This command is used to turn ON the Tearing Effect output signal from the TE signal line. -This output is not affected by changing MADCTR bit ML. -The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. ("-"=Don't Care). When M='0': The Tearing Effect Output line consists of V-Blanking information only. Description Vertical time scale When M='1': re The Tearing Effect Output line consists of both V-Blanking and H-Blinking information. nd .co tvdl tvdl m Availability Yes Yes Yes Yes Yes tvdh tvdh Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w w Status Restriction -This command has no effect when Tearing Effect output is already OFF. .m Vertical time scale bt Default Value RCM1, RCM0 = "00", "1x" RCM1, RCM0 = "01" OFF & TELOM=0 ON & TELOM=0 Default Power On Sequence S/W Reset H/W Reset Legend TE Line Output OFF Command Parameter Flow Chart TEON (35H) 1st Parameter: TELOM Display Action Mode Sequential transfer TE Line Output ON (c) ORISE Technology Co., Ltd. Proprietary & Confidential 63 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.29. MADCTR (36H): Memory Data Access Control 36H Inst / Para MADCTR st MADCTR (Memory Data Access Control) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 MX D5 1 MV D4 1 ML D3 0 RGB D2 1 MH D1 1 0 D0 0 0 (Code) (36H) 00h 1 Parameter 1 1 MY NOTE: "-" Don't care, can be set to VDDI or DGND level -This command defines read/ write scanning direction of frame memory. -This command makes no change on the other driver status. -Bit Assignment Bit MY MX MV ML RGB NAME Row Address Order Column Address Order Row/Column Exchange Vertical Refresh Order RGB-BGR ORDER DESCRIPTION ML: Vertical Refresh Order Top-Left (0,0) Memory bt RGB re Sent First Sent 2nd Sent 3rd Sent Last Sent Last Sent 3rd Sent 2nd Sent First w Description Top-Left (0,0) w w .m Memory ML='0' ML='1' RGB: RGB-BGR Order RGB="0" Driver IC RGB RGB RGB nd .co RGB RGB BGR BGR 64 LCD vertical refresh direction control `0' = LCD vertical refresh Top to Bottom `1' = LCD vertical refresh Bottom to Top Color selector switch control `0' =RGB color filter panel, `1' =BGR color filter panel) Display Display m RGB BGR BGR These 3bits controls MCU to memory write/read direction. (See Section 8.11) RGB="1" Driver IC RGB RGB RGB RGB RGB BGR BGR LCD Panel LCD Panel Restriction D1 and D0 of the 1 parameter are set to "00" internally. st (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Default Status Power On Sequence S/W Reset H/W Reset Default Value MY=0,MX=0,MV=0,ML=0,RGB=0, No Change MY=0,MX=0,MV=0,ML=0,RGB=0, m nd .co re bt 65 Legend Command MADCTR (36H) Flow Chart Parameter Display 1 Parameter: MY, MX, ML, RGB st Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.30. VSCSAD (37H): Vertical Scroll Start Address of RAM 37H Inst / Para VSCSAD 1 Parameter nd st VSCSAD (Vertical Scroll Start Address of RAM) D/CX 0 1 WRX RDX 1 1 D17-8 D7 0 D6 0 SSA6 D5 1 SSA5 D4 1 SSA4 D3 0 SSA3 D2 1 SSA2 D1 1 SSA9 SSA1 D0 1 SSA8 SSA0 (Code) (37h) SSA15 SSA14 SSA13 SSA12 SSA11 SSA10 2 Parameter 1 1 SSA7 NOTE: "-" Don't care, can be set to VDDI or DGND level -This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. -The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: -Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h). (Example) Memory re 0 1 2 3 158 159 159 158 3 2 1 0 Top-Left (0,0) nd .co Scan address Scan address When MADCTR ML= `0' Example: When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=220 and Vertical Scrolling Pointer SSA= '3'. m G1 G2 G3 G4 | | G159 G160 G1 G2 G3 G4 | | G159 G160 -This command Start the scrolling. Display w When MADCTR ML = `1' Example: When Top Fixed Area= Bottom Fixed Area=00, Vertical Scrolling Area=220 and SSA= '3' w w (Example) Top-Left (0,0) Description .m Memory SSA[15:0] Scroll start address bt Display SSA[15:0] Scroll start address NOTE: -When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. -SSA refers to the Frame Memory scan address. -Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h)-otherwise undesirable image will be displayed on the Panel. Restriction SSA[15:0] is based on 1-line unit. -SSA[15:0] = 0000h, 0001h, 0002h, 0003h, ... , 00A1h (c) ORISE Technology Co., Ltd. Proprietary & Confidential 66 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes No No Yes Register Availability Default Status Power On Sequence S/W Reset H/W Reset See Vertical Scrolling Definition (33h) description. Default Value 0000h 0000h 0000h Flow Chart (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 67 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.31. IDMOFF (38H): Idle Mode Off 38H Inst / Para IDMOFF st IDMOFF (Idle Mode Off) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 (Code) (38H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command is used to recover from Idle mode on. -There will be no abnormal visible effect on the display mode change transition. Description -In the idle off mode, 1. LCD can display 4k, 65k and 262k -colors. 2. Normal frame frequency is applied. Register Availability Default w .m Status Power On Sequence S/W Reset H/W Reset re bt nd .co 68 Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In m Restriction -This command has no effect when module is already in idle off mode. Availability Yes Yes Yes Yes Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off Legend Command w Idle mode ON w Parameter Display Flow Chart IDMOFF (38) Action Idle mode OFF Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.32. IDMON (39H): Idle Mode On 39H Inst / Para IDMON st IDMON (Idle Mode On) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1 (Code) (39H) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter -This command is used to enter into Idle mode on. -There will be no abnormal visible effect on the display mode change transition. -In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38H) command Top-Left (0,0) Memory bt 69 re This command has no effect when module is already in idle on mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off Description nd .co Display "x" Don't care B5 B4 B3 B4 B1 B0 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx (Example) Restriction Register Availability Default (c) ORISE Technology Co., Ltd. Proprietary & Confidential w Color Black Blue Red Magenta Green Cyan Yellow White R5 R4 R3 R2 R1 R0 0xxxxx 0xxxxx 1xxxxx 1xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx G5 G4 G3 G2 G1 G0 0xxxxx 0xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx 1xxxxx 1xxxxx w w .m m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Legend Command Idle mode OFF Parameter Display Flow Chart IDMOFF (39) Action Mode Idle mode ON Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 70 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.33. COLMOD (3AH): Interface Pixel Format 3AH Inst / Para COLMOD st COLMOD (Interface Pixel Format) D/CX 0 WRX RDX 1 D17-8 D7 0 D6 0 VIPF2 D5 1 VIPF1 D4 1 VIPF0 D3 1 D3 D2 0 IFPF2 D1 1 IFPF1 D0 0 IFPF0 (Code) (3AH) 66h 1 Parameter 1 1 VIPF3 NOTE: "-" Don't care, can be set to VDDI or DGND level Description w w Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m Restriction There is no visible effect until the Frame Memory is written to. Availability Yes Yes Yes Yes Yes Status Default Power On Sequence S/W Reset H/W Reset Example: w bt RGB Interface Color Format 16-bits/pixel (1-times data transfer) 18-bits/pixel (1-times data transfer) Reserved 18-bits/pixel (3-times data transfer) Others are no define and invalid Note1: In 12-bits/Pixel, 16-bits/Pixel or 18-bits/Pixel mode, the LUT is applied to transfer data into the Frame Memory. Note2: When RGB I/F the 12-bit/pixel don't care Note 3: When VIPF[3:0]="1110",6-bits data width of 3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information. VIPF[3:0] 0101 5 0110 6 0111 7 1110 14 re nd .co Default Value IFPF[2:0] VIPF[3:0] 0101 (16-bits/pixel) 0110 (18-bits/pixel) No Change No Change 0101 (16-bits/pixel) 0110 (18-bits/pixel) m This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface and RGB interface. The formats are shown in the table: IFPF[2:0] MCU Interface Color Format 011 3 12-bits/pixel 101 5 16-bits/pixel 110 6 18-bits/pixel 111 7 Reserved Others are no define and invalid Legend 16-bits/Pixel Mode Command Parameter COLMOD (3AH) Flow Chart 1 Parameter st Display Action Mode Sequential transfer 18-bits/Pixel Mode (c) ORISE Technology Co., Ltd. Proprietary & Confidential 71 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.34. RDID1 (DAH): Read ID1 Value DAH Inst / Para RDID1 1 Parameter nd st RDID1 (Read ID1 Value) D/CX 0 1 WRX 1 RDX 1 D17-8 D7 1 D6 1 ID16 D5 0 ID15 D4 1 ID14 D3 1 ID13 D2 0 ID12 D1 1 ID11 D0 0 ID10 (Code) (DAH) 38h 2 Parameter 1 1 ID17 NOTE: "-" Don't care, can be set to VDDI or DGND level -This read byte returns 8-bits LCD module's manufacturer ID Description -The 1 parameter is dummy data -The 2 parameter (ID17 to ID10): LCD module's manufacturer ID. nd NOTE: See command RDDID (04H), 2 parameter. nd st Register Availability Default w .m Status Power On Sequence S/W Reset H/W Reset re bt nd .co RDID1 (DAH) Dummy Read nd Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In m 72 Restriction Availability Yes Yes Yes Yes Yes Default Value 38h 38h 38h w Serial I/F Mode Partial I/F Mode Host Driver Legend Command w RDID1 (DAH) Parameter Display Flow Chart Send 2 parameter: ID1[7:0] nd Action Mode Send 2 parameter: ID1[7:0] Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.35. RDID2 (DBH): Read ID2 Value DBH Inst / Para RDID2 1 Parameter nd st RDID2 (Read ID2 Value) D/CX 0 1 WRX 1 RDX 1 D17-8 D7 1 D6 1 ID26 D5 0 ID25 D4 1 ID24 D3 1 ID23 D2 0 ID22 D1 1 ID21 D0 1 ID20 (Code) (DBH) 80h 2 Parameter 1 1 ID27 NOTE: "-" Don't care, can be set to VDDI or DGND level -This read byte returns 8-bits LCD module/driver version ID Description -The 1 parameter is dummy data -The 2 parameter (ID26 to ID20): LCD module/driver version ID rd NOTE: See command RDDID (04H), 3 parameter. nd st Register Availability Default w .m Status Power On Sequence S/W Reset H/W Reset re bt nd .co Partial I/F Mode RDID2 (DBH) Dummy Read Send 2 parameter: ID2[7:0] nd Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In m 73 Restriction Availability Yes Yes Yes Yes Yes Default Value 80h 80h 80h Serial I/F Mode RDID2 (DBH) Legend Command w w Host Driver Parameter Display Flow Chart Send 2 parameter: ID2[7:0] nd Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.36. RDID3 (DCH): Read ID3 Value DCH Inst / Para RDID3 1 Parameter nd st RDID3 (Read ID2 Value) D/CX 0 1 WRX 1 RDX 1 D17-8 D7 1 D6 1 ID36 D5 0 ID35 D4 1 ID34 D3 1 ID33 D2 1 ID32 D1 0 ID31 D0 0 ID30 (Code) (DCH) 62h 2 Parameter 1 1 ID37 NOTE: "-" Don't care, can be set to VDDI or DGND level -This read byte returns 8-bits LCD module/driver ID. Description -The 1 parameter is dummy data -The 2 parameter (ID37 to ID30): LCD module/driver ID. th NOTE: See command RDDID (04H), 4 parameter. nd st Register Availability Default w .m Status Power On Sequence S/W Reset H/W Reset re bt nd .co RDID3 (DCH) Dummy Read nd Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In m 74 Restriction - Availability Yes Yes Yes Yes Yes Default Value 62h 62h 62h w Serial I/F Mode RDID3 (DCH) Flow Chart Partial I/F Mode Host Driver Legend Command w Parameter Display Send 2 parameter: ID3[7:0] nd Action Mode Send 2 parameter: ID3[7:0] Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.37. SRGBOFF (AAH): Separate RGB Gamma OFF AAH Inst / Para SRGBOFF st SRGBOFF (Separate RGB Gamma OFF) D/CX 0 WRX RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 1 D0 0 (Code) (AAH) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn OFF the separate RGB gamma function. -This command has no effect when separate RGB gamma function OFF. Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Default Value RCM1, RCM0 = "00", "1x" RCM1, RCM0 = "01" ON .m bt m Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Legend Command w Separate RGB gamma ON w Parameter Display Flow Chart w SRGBOFF (AAH) Action Mode Sequential transfer Separate RGB gamma OFF (c) ORISE Technology Co., Ltd. Proprietary & Confidential 75 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.38. SRGBOFF (ABH): Separate RGB Gamma ON ABH Inst / Para SRGBON st SRGBOFF (Separate RGB Gamma ON) D/CX 0 WRX RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 1 D0 1 (Code) (ABH) - 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn On the separate RGB gamma function. -In this mode, It only the gamma curve 2.2 (GC0) can be separated to R, G, and B gamma curve -This command has no effect when separate RGB gamma function ON. Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value RCM1, RCM0 = "00", "1x" RCM1, RCM0 = "01" ON .m bt m w Separate RGB gamma OFF w Legend Command Parameter Display Flow Chart w SRGBON (ABH) Action Separate RGB gamma ON Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 76 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.39. VSYNCOFF (ACH): VSYNC Interface OFF ACH Inst / Para VSYNCOFF st VSYNCOFF (VSYNC Interface OFF) D/CX 0 WRX RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 0 (Code) (ACH) -- 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn OFF the VSYNC interface function. -This command has no effect when VSYNC interface OFF. -Input Vs signal for more than 1 frame period after turn OFF the VSYNC I/F Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value RCM1, RCM0 = "00", "1x" RCM1, RCM0 = "01" ON .m bt m VSYNC Interface function ON w Legend Command w w VSYNCOFF (ACH) Wait more than 1 frame Parameter Display Flow Chart Action Mode Sequential transfer VSYNC Interface function OFF Input Vs signal foe more than 1 frame period after turn OFF the VSYNC I/F (c) ORISE Technology Co., Ltd. Proprietary & Confidential 77 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.40. VSYNCON (ADH): VSYNC Interface ON ADH Inst / Para VSYNCON st VSYNCOFF (VSYNC Interface ON) D/CX 0 WRX RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 1 (Code) (ADH) -- 1 Parameter NOTE: "-" Don't care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn ON the VSYNC interface function. -This command has no effect when VSYNC interface ON. -Input VS signal before turn On the VSYNC I/F Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value RCM1, RCM0 = "00", "1x" RCM1, RCM0 = "01" ON .m bt m VSYNC Interface function OFF w Legend Command w w VSYNCON (ADH) Wait more than 1 frame Parameter Display Flow Chart Action Mode VSYNC Interface function ON Sequential transfer Note: Input VS signal before turn On the VSYNC I/F (c) ORISE Technology Co., Ltd. Proprietary & Confidential 78 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.41. VSCTR1 (AEH): VSYNC Interface function control 1 AEH Inst / Para VSCTR1 st VSYNCTR1 (VSYNC Interface function control 1) D/CX 0 WRX RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 1 (Code) (AEH) 2Eh 1 Parameter 1 VSFP3 VSFP2 VSFP1 VSFP0 VSBP3 VSBP2 VSBP1 VSBP0 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -Set the back porch and front porch on the VSYNC interface. The setting becomes effective as soon as the command is received. -VSFP: Front porch set on VSYNC I/F -VSBP: Back porch set on VSYNC I/F VSBP[3:0] Front porch period (Line) VSFP[3:0] 0000 0 Setting inhibited 0001 1 Setting inhibited 0010 2 2-lines 0011 3 3-lines 0100 4 4-lines 0101 5 5-lines 0110 6 6-lines 0111 7 7-lines 1000 8 8-lines 1001 9 9-lines 1010 10 10-lines 1011 11 11-lines 1100 12 12-lines 1101 13 13-lines 1110 14 14-lines 1111 15 Setting inhibited Description Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w Restriction -The command is enabled by VSYNCON (ADH) Availability Yes Yes Yes Yes Yes w Status Default Power On Sequence S/W Reset H/W Reset VSFP[3:0] 2d No Change 2d w Setting inhibited Setting inhibited 2-lines 3-lines 4-lines 5-lines 6-lines 7-lines 8-lines 9-lines 10-lines 11-lines 12-lines 13-lines 14-lines Setting inhibited .m bt re nd .co Default Value VSBP[3:0] 14d No Change 14d m Back porch period (Line) -----------------VSCTR1 (AEH) Legend Command Parameter Display Flow Chart 1st Parameter: VSFP[3:0], VSBP[3:0] Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 79 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3. Panel Command Description 6.3.1. RGBCTR (B0H): RGB signal control B0H Inst / Para RGBCTR st RGBCTR (RGB signal control) D/CX 0 WRX RDX 1 D17-8 D7 1 0 D6 0 0 D5 1 0 D4 1 ICM D3 0 DP D2 0 EP D1 0 HSP D0 0 VSP (Code) (B0H) 00h 1 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -Set the operation status on the RGB interface. The setting becomes effective as soon as the command is received. -ICM: GRAM Write/Read frequency and data input select on the RGB interface ICM Write/ Read frequency and input data select Write cycle Read cycle Data input 0 PCLK PCLK D[B:0] 1 SCL Internal oscillator SDA B=17 Description Symbol DP EP HSP VSP Name PCLK polarity set Enable polarity set Hsync polarity set Vsync polarity set Clock polarity set for RGB Interface `1' = data fetched at the falling edge `0' = data fetched at the rising edge `1' = Low enable for RGB interface `0' = High enable for RGB interface `1' = High level sync clock `0' = Low level sync clock `1' = High level sync clock `0' = Low level sync clock -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w Restriction .m bt re ICM 0d 0d 0d Register Availability w Status Default Power On Sequence S/W Reset H/W Reset nd .co Default Value DP/EP/HSP/VSP 0d/0d/0d/0d 0d/0d/0d/0d 0d/0d/0d/0d -----------------RGBCTR (B0H) m Availability Yes Yes Yes Yes Yes Legend Command Parameter Display Flow Chart 1st Parameter: ICM, DP, EP, HSP, VSP Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 80 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.2. FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors) B1H Inst / Para FRMCTR1 1 Parameter 2 Parameter 3 Parameter NOTE: "-" Don't care rd nd st FRMCTR1 (Frame Rate Control) D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D7 1 0 0 0 D6 0 0 0 0 D5 1 0 0 0 D4 1 0 0 0 D3 0 FP0[3] BP0[3] RTN0 [3] D2 0 FP0[2] BP0[2] RTN0 [2] D1 0 FP0[1] BP0[1] RTN0 [1] D0 1 FP0[0] BP0[0] RTN0 [0] (Code) (B1h) - -Set the frame frequency of the full colors normal mode in MPU interface. --The default vaule of BP0, FP0, and RTN0 can fit the frame frequency to be 65Hz 5%. FP0[3:0] 0 1 2 3 4 ... D E F BP0[3:0] 0 1 2 3 4 ... D E F Amount of Front Porch 0 1 2 3 4 ... 13 14 15 Description RTN0[3:0] 0 1 2 3 4 ... D E F Restriction w w w .m FP0 2d 2d 2d -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset bt Amount of Back Porch 0 1 2 3 4 ... 13 14 15 No. of clock in one line 16 17 18 19 20 ... 29 30 31 re nd .co Default Value BP0 14d 14d 14d RTN0 0d 0d 0d (c) ORISE Technology Co., Ltd. Proprietary & Confidential 81 m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B ------------FRMCTR1 (B1h) Legend Command Parameter Display Flow Chart 1 Parameter: FP0 [3:0] nd 2 Parameter: BP0 [3:0] 3rd Parameter: RTN0 [3:0] st Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 82 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.3. FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors) B2H Inst / Para FRMCTR2 1 Parameter 2 Parameter 3 Paramete NOTE: "-" Don't care rd nd st FRMCTR2 (Frame Rate Control) D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D7 1 0 0 0 D6 0 0 0 0 D5 1 0 0 0 D4 1 0 0 0 D3 0 FP1[3] BP1[3] RTN1 [3] D2 0 FP1[2] BP1[2] RTN1 [2] D1 1 FP1[1] BP1[1] RTN1 [1] D0 0 FP1[0] BP1[0] RTN1 [0] (Code) (B2h) - -Set the frame frequency of the Idle mode in MPU interface. -The default vaule of BP1, FP1, and RTN1 can fit the frame frequency to be 70Hz 5%. FP1[3:0] 0 1 2 3 4 ... D E F BP1[3:0] 0 1 2 3 4 ... D E F Amount of Front Porch 0 1 2 3 4 ... 13 14 15 Description RTN1[3:0] 0 1 2 3 4 ... D E F Restriction w w w .m FP1 2d 2d 2d -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset bt Amount of Back Porch 0 1 2 3 4 ... 13 14 15 No. of clock in one line 16 17 18 19 20 ... 29 30 31 re nd .co Default Value BP1 14d 14d 14d RTN1 0d 0d 0d (c) ORISE Technology Co., Ltd. Proprietary & Confidential 83 m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B ------------FRMCTR2 (B2h) Legend Command Parameter Display Flow Chart 1 Parameter: FP1 [3:0] nd 2 Parameter: BP1 [3:0] 3rd Parameter: RTN1 [3:0] st Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 84 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.4. FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors) B3H Inst / Para FRMCTR3 1 Parameter 2 Parameter 3 Parameter NOTE: "-" Don't care rd nd st FRMCTR3 (Frame Rate Control) D/CX 0 1 1 1 WRX RDX 1 1 1 1 D17-8 D7 1 0 0 0 D6 0 0 0 0 D5 1 0 0 0 D4 1 0 0 0 D3 0 FP2[3] BP2[3] RTN2 [3] D2 0 FP2[2] BP2[2] RTN2 [2] D1 1 FP2[1] BP2[1] RTN2 [1] D0 1 FP2[0] BP2[0] RTN2 [0] (Code) (B3h) - -Set the frame frequency of the Partial mode/ full colors in MPU interface. -The default vaule of BP2, FP2, and RTN2 can fit the frame frequency to be 70Hz 5% with frame inversion Description BP2[3:0] 0 1 2 3 4 ... D E F .m w w w FP2 2d 2d 2d RTN2[3:0] 0 1 2 3 4 ... D E F Restriction -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset bt FP2[3:0] 0 1 2 3 4 ... D E F Amount of Front Porch 0 1 2 3 4 ... 13 14 15 Amount of Back Porch 0 1 2 3 4 ... 13 14 15 No. of clock in one line 16 17 18 19 20 ... 29 30 31 re nd .co Default Value BP2 14d 14d 14d RTN2 0d 0d 0d (c) ORISE Technology Co., Ltd. Proprietary & Confidential 85 m Apr. 25, 2006 Preliminary Version: 0.1 and 65Hz 5% with line inversion in this mode Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B ------------FRMCTR3 (B3h) Legend Command Parameter Display Flow Chart 1 Parameter: FP2 [3:0] nd 2 Parameter: BP2 [3:0] 3rd Parameter: RTN2 [3:0] st Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 86 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.5. INVCTR (B4h): Display Inversion Control B4H Inst / Para INVCTR st INVCTR (Display Inversion Control) D/CX 0 WRX RDX 1 D17-8 D7 1 0 D6 0 0 D5 1 0 D4 1 0 D3 0 0 D2 1 NLA D1 0 NLB D0 0 NLC (Code) (B4h) 1 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -Display Inversion mode control -NLA: Inversion setting in full colors normal mode (Normal mode on) NLA Inversion setting in full colours normal mode 0 Line Inversion 1 Frame Inversion -NLB: Inversion setting in Idle mode (Idle mode on) NLB Inversion setting in Idle mode 0 Line Inversion 1 Frame Inversion Description Restriction -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Status Default Power On Sequence S/W Reset H/W Reset NLA 0d 0d 0d NLB 1d 1d 1d w w Register Availability w .m bt -NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off) NLC Inversion setting in full colours partial mode 0 Line Inversion 1 Frame Inversion re nd .co Default Value m NLC 0d 0d 0d B4h 02h 02h 02h ------------INVCTR (B4h) Legend Command Parameter Display Flow Chart 1 Parameter: st Action Mode Sequential transfer NLA, NLB, NLC (c) ORISE Technology Co., Ltd. Proprietary & Confidential 87 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.6. RGBBPCTR (B5h): RGB Interface Blanking Porch setting B5H Inst / Para RGBBPCTR 1 Parameter NOTE: "-" Don't care st RGBPSET (RGB Interface Blanking Porch setting) D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1 (Code) (B5h) - VBP[3] VBP[2] VBP[1] VBP[0] -Set the blanking porch in the RGB interface VBP[3:0] 0 1 2 3 4 ... D E F Amount of Back Porch in RGB interface 0 1 2 3 4 ... 13 14 15 Description Restriction -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset w .m bt Register Availability re w w ---------------RGBBPCTR (B3h) nd .co Default Value VBP 3d 3d 3d m Availability Yes Yes Yes Yes Yes Legend Command Parameter Display Flow Chart 1 Parameter: VBP [3:0] st Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 88 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.7. DISSET5 (B6h): Display Function set 5 B4H Inst / Para DISSET5 1 Parameter nd 2 Parameter NOTE: "-" Don't care st st DISSET (Display Function set 5) D/CX 0 1 1 WRX RDX 1 1 1 D17-8 D7 1 0 0 D6 0 0 0 D5 1 NO1 0 D4 1 NO0 0 D3 0 SDT1 PTG1 D2 1 STD0 PTG0 D1 1 EQ1 PT1 D0 0 EQ0 PT0 (Code) (B6h) -1 parameter: Set output waveform relation. -NO[1:0]: Set the amount of non-overlap of the gate output NO[1:0] Amount of non-overlap of the gate output Refer the Internal oscillator Refer the PCLK 00 0 1 clock cycle 4 clock cycle 01 1 4 clock cycle 16 clock cycle 10 2 6 clock cycle 24 clock cycle 11 3 8 clock cycle 32 clock cycle -SDT[1:0]: Set delay amount from gate signal falling edge of the source output. SDT[1:0] Amount of non-overlap of the source output Refer the Internal oscillator Refer the PCLK 00 0 1 clock cycle 4 clock cycle 01 1 2 clock cycle 8 clock cycle 10 2 3 clock cycle 12 clock cycle 11 3 4 clock cycle 16 clock cycle -EQ[1:0]: Set the Equalizing period EQ[1:0] EQ period Refer the Internal oscillator 00 0 No EQ 01 1 2 clock cycle 10 2 4 clock cycle 11 3 6 clock cycle .m bt 89 re w w Description Gn Gn+1 Sn VCOM -2 parameter: Set the output waveform in non-display area. -PTG[1:0]: Determine gate output in a non-display area in the partial mode PTG[1:0] Gate output in a non-display area 00 0 Normal scan 01 1 Fix on VGL 10 2 Fix on VGL 11 3 Fix on VGL -PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode Source output on non-display VCOM output on non-display PT[1:0] area area Positive Negative Positive Negative 00 0 V63 V0 VCOML VCOMH 01 1 V0 V63 VCOML VCOMH 10 2 AGND AGND AGND AGND 11 3 Hi-z Hi-z AGND AGND nd (c) ORISE Technology Co., Ltd. Proprietary & Confidential w Gate Non-overlap period Delay time for source output EQ period nd .co Refer the PCLK No EQ 4 clock cycle 16 clock cycle 24 clock cycle m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Restriction -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset NO[1:0] 1d 1d 1d STD[1:0] 1d 1d 1d Default Value EQ[1:0] 2d 2d 2d PTG[1:0] 0d 0d 0d PT[1:0] 2d 2d 2d -----------------DISSET5 (B6h) m nd .co 90 Legend Command Parameter Display re Flow Chart bt 1 Parameter: NO[1:0], STD[1:0], EQ[1:0] nd 2 Parameter: PTG[1:0], PT[1:0] st Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.8. PWCTR1 (C0H): Power Control 1 C0H Inst / Para PWCTR1 1 Parameter nd st PWCTR1 (Power Control 1) D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 0 0 D6 1 0 0 D5 0 0 0 D4 0 VRH4 0 D3 0 VRH3 0 D2 0 VRH2 VCI2 D1 0 VRH1 VCI1 D0 0 VRH0 VCI0 (Code) (C0H) 05h 05h 2 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -Set the GVDD and VCI1 voltage VRH[4:0] 00000 0 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 29 11110 30 11111 31 GVDD 5.00 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 3.75 3.70 3.65 3.60 3.55 3.50 3.45 3.40 3.35 3.25 3.00 VC[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 VCI1 2.75 2.70 2.65 2.60 2.55 2.50 2.80 2.90 Description -If this register not using the register need be reserved. Restriction -The deviation value of GVDD between with Measurement and Specification: Max <=50mV -The deviation value of VCI1 between with Measurement and Specification: Max <=2% deviation Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 91 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Status Default Value LCM = `01' LCM = `11' TM LC Type ECB LC type VRH[4:0] VC[2:0] VRH[4:0] VC[2:0] 5d 5d 5d 5d 5d 5d 5d 5d 5d 5d 5d 5d Default Power On Sequence S/W Reset H/W Reset -------------PWCTR1 (C0H) Legend Command Parameter 1st Parameter: VRH[4:0] 2 nd Flow Chart m nd .co re 92 Display Action Mode Sequential transfer Parameter: VCI[2:0] (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.9. PWCTR2 (C1H): Power Control 2 C1H Inst / Para PWCTR2 st PWCTR2 (Power Control 2) D/CX 0 WRX RDX 1 D17-8 D7 1 0 D6 1 0 D5 0 0 D4 0 0 D3 0 0 D2 0 BT2 D1 0 BT1 D0 1 BT0 (Code) (C1H) 07h 1 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -Set the AVDD, VCL, VGH and VGL supply power level BT[2:0] 000 0 001 1 010 011 100 101 110 111 2 3 4 5 6 7 AVDD 2xVDDI 4.75 2xVDDI 4.75 2xVDDI 2xVDDI 2xVDDI 2xVDDI 2xVDDI 2xVDDI 4.75 4.75 4.75 4.75 4.75 4.75 VCL -1xVDDI -2.45 -1xVDDI -2.45 -1xVDDI -1xVDDI -1xVDDI -1xVDDI -1xVDDI -1xVDDI -2.45 -2.45 -2.45 -2.45 -2.45 -2.45 VGH 4*VDDI 9.80 4*VDDI 9.80 5*VDDI 5*VDDI 5*VDDI 6*VDDI 6*VDDI 6*VDDI 12.25 12.25 12.25 14.70 14.70 14.70 VGL -3*VDDI -7.35 -4*VDDI -9.80 -3*VDDI -4*VDDI -5*VDDI -3*VDDI -4*VDDI -5*VDDI -7.35 -9.80 -12.25 -7.35 -9.80 -12.25 Note: When VCI1=2.5V, Set-up cycle 1 effective=95%, Set-up cycle 2 effective=98%, -If this register not using the register need be reserved. Restriction -VGH-VGL <= 25V -The deviation value of VGH/ VGL between with Measurement and Specification: Max: VGH-VGL<=1V Status Default w w w Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In bt Default Value BT[2:0] 7d 7d 7d re Power On Sequence S/W Reset H/W Reset --------------PWCTR2 (C1H) .m nd .co m Description Availability Yes Yes Yes Yes Yes Legend Command Parameter Display Flow Chart st 1 Parameter: BT[2:0] Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential 93 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.10. PWCTR3 (C2H): Power Control 3 (in Normal mode/ Full colors) C2H Inst / Para PWCTR3 st PWCTR3 (Power Control 3) D/CX 0 WRX RDX 1 D17-8 D7 1 0 0 D6 1 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 APA2 DCA2 D1 1 APA1 DCA1 D0 0 APA0 DCA0 (Code) (C2H) 01h 1 Parameter 1 1 nd 2 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -Set the amount of current in Operational amplifier in normal mode/full colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. AP[2:0] 000 001 010 011 100 101 110 111 Description 0 1 2 3 4 5 6 7 Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved -Set the Booster circuit Step-up cycle in Normal mode/ full colors. DC[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 1 BCLK / 1 BCLK / 1 BCLK / 1 BCLK / 2 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 4 Step-up cycle in Booster circuit 2,3 BCLK / 1 BCLK / 2 BCLK / 4 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 8 BCLK / 16 Note: BCLK is Clock frequency for Booster circuit Restriction -If some parameters of the register not use the register need to be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 94 re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. 176x220 memory base (GM1, GM0 = "00") Status AP[2:0] Power On Sequence 4d S/W Reset No Change H/W Reset 4d 2. 176x176 memory base (GM1, GM0 = "01") Status AP[2:0] Power On Sequence 4d S/W Reset No Change H/W Reset 4d 3. 176x132 memory base (GM1, GM0 = "11") Status AP[2:0] Power On Sequence 3d S/W Reset No Change H/W Reset 3d Default Value DC[2:0] 1d No Change 1d Default Value DC[2:0] 1d No Change 1d Default Value DC[2:0] 1d No Change 1d Default --------------PWCTR3 (C2H) nd .co re 95 m Legend Command Parameter Display Flow Chart .m 1st Parameter: APA[2:0] 2 nd bt Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w Parameter: DCA[2:0] Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.11. PWCTR4 (C3H): Power Control 4 (in Idle mode/ 8-colors) C3H Inst / Para PWCTR4 st PWCTR4 (Power Control 4) D/CX 0 WRX RDX 1 D17-8 D7 1 0 0 D6 1 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 APB2 DCB2 D1 1 APB1 DCB1 D0 1 APB0 DCB0 (Code) (C3H) 04h 1 Parameter 1 1 nd 2 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -Set the amount of current in Operational amplifier in Idle mode/ 8-colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. AP[2:0] 000 001 010 011 100 101 110 111 Description 0 1 2 3 4 5 6 7 Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved -Set the Booster circuit Step-up cycle in Idle mode/ 8-colors. DC[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Note: BCLK is Clock frequency for Booster circuit Restriction -If some parameters of the register not use the register need to be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability (c) ORISE Technology Co., Ltd. Proprietary & Confidential w Step-up cycle in Booster circuit 1 BCLK / 1 BCLK / 1 BCLK / 1 BCLK / 2 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 4 re 96 w w .m bt nd .co Step-up cycle in Booster circuit 2,3 BCLK / 1 BCLK / 2 BCLK / 4 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 8 BCLK / 16 m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. 176x220 memory base (GM1, GM0 = "00") Status AP[2:0] Power On Sequence 2d S/W Reset 2d H/W Reset 2d 2. 176x176 memory base (GM1, GM0 = "01") Status AP[2:0] Power On Sequence 2d S/W Reset 2d H/W Reset 2d 3. 176x132 memory base (GM1, GM0 = "11") Status AP[2:0] Power On Sequence 2d S/W Reset 2d H/W Reset 2d Default Value DC[2:0] 4d 4d 4d Default Value DC[2:0] 4d 4d 4d Default Value DC[2:0] 4d 4d 4d Default --------------PWCTR4 (C3H) nd .co re 97 m Legend Command Parameter Display Flow Chart .m 1st Parameter: APB[2:0] 2 nd bt Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w Parameter: DCB[2:0] Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.12. PWCTR5 (C4H): Power Control 5 (in Partial mode/ full-colors) C4H Inst / Para PWCTR5 st PWCTR5 (Power Control 5) D/CX 0 WRX RDX 1 D17-8 D7 1 0 0 D6 1 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 1 APC2 DCC2 D1 0 APC1 DCC1 D0 0 APC0 DCC0 (Code) (C4H) 03h 02h 1 Parameter 1 1 nd 2 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -Set the amount of current in Operational amplifier in Partial mode/ full-colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver. AP[2:0] 000 001 010 011 100 101 110 111 Description 0 1 2 3 4 5 6 7 Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved -Set the Booster circuit Step-up cycle in Partial mode/ full-colors. DC[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 Step-up cycle in Booster circuit 1 BCLK / 1 BCLK / 1 BCLK / 1 BCLK / 2 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 4 Step-up cycle in Booster circuit 2,3 BCLK / 1 BCLK / 2 BCLK / 4 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 8 BCLK / 16 Note: BCLK is Clock frequency for Booster circuit Restriction -If some parameters of the register not use the register need to be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 98 re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. 176x220 memory base (GM1, GM0 = "00") Status APC[2:0] Power On Sequence 4d S/W Reset 4d H/W Reset 4d 2. 176x176 memory base (GM1, GM0 = "01") Status APC[2:0] Power On Sequence 4d S/W Reset 4d H/W Reset 4d 3. 176x132 memory base (GM1, GM0 = "11") Status APC[2:0] Power On Sequence 3d S/W Reset 3d H/W Reset 3d Default Value DCC[2:0] 2d 2d 2d Default Value DCC[2:0] 2d 2d 2d Default Value DCC[2:0] 2d 2d 2d Default --------------PWCTR5 (C4H) nd .co re 99 m Legend Command Parameter Display Flow Chart .m 1st Parameter: APC[2:0] 2 nd bt Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w Parameter: DCC[2:0] Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.13. VMCTR1 (C5H): VCOM Control 1 C5H Inst / Para VMCTR1 st VMCTR1 (VCOM Control 1) D/CX 0 WRX RDX 1 D17-8 D7 1 D6 1 VMH6 D5 0 VMH5 D4 0 D3 0 D2 1 D1 0 D0 1 (Code) (C5h) 1 Parameter 1 nVM * 1 NOTE: "-" Don't care, can be set to VDDI or DGND level VMH 4 VMH 3 VMH 2 VMH 1 VMH 0 -Set VCOMH Voltage VMH[6:0] 0000000 0 0000001 1 0000010 2 0000011 3 0000100 4 0000101 5 0000110 6 0000111 7 0001000 8 0001001 9 0001010 10 0001011 11 0001100 12 0001101 13 0001110 14 0001111 15 0010000 16 0010001 17 0010010 18 0010011 19 0010100 20 0010101 21 0010110 22 0010111 23 0011000 24 0011001 25 0011010 26 VCOMH 2.500 2.525 2.550 2.575 2.600 2.625 2.650 2.675 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050 3.075 3.100 3.125 3.150 VMH[6:0] 0011011 27 0011100 28 0011101 29 0011110 30 0011111 31 0100000 32 0100001 33 0100010 34 0100011 35 0100100 36 0100101 37 0100110 38 0100111 39 0101000 40 0101001 41 0101010 42 0101011 43 0101100 44 0101101 45 0101110 46 0101111 47 0110000 48 0110001 49 0110010 50 0110011 51 0110100 52 0110101 53 VCOMH 3.175 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 3.500 3.525 3.550 3.575 3.600 3.625 3.650 3.675 3.700 3.725 3.750 3.775 3.800 3.825 VMH[6:0] 0110110 54 0110111 55 0111000 56 0111001 57 0111010 58 0111011 59 0111100 60 0111101 61 0111110 62 0111111 63 1000000 64 1000001 65 1000010 66 1000011 67 1000100 68 1000101 69 1000110 70 1000111 71 1001000 72 1001001 73 1001010 74 1001011 75 1001100 76 1001101 77 1001110 78 1001111 79 1010000 80 VCOMH 3.850 3.875 3.900 3.925 3.950 3.975 4.000 4.025 4.050 4.075 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 4.325 4.350 4.375 4.400 4.425 4.450 4.475 4.500 VMH[6:0] VCOMH 1010001 81 4.525 1010010 82 4.550 1010011 83 4.575 1010100 84 4.600 1010101 85 4.625 1010110 86 4.650 1010111 87 4.675 1011000 88 4.700 1011001 89 4.725 1011010 90 4.750 1011011 91 4.775 1011100 92 4.800 1011101 93 4.825 1011110 94 4.850 1011111 95 4.875 1100000 96 4.900 1100001 97 4.925 1100010 98 4.950 1100011 99 4.975 1100100 100 5.000 1100101 101 Not | Permitted 1111111 127 -Select the VCOMH value nVM * 0 1 VCOMH value VCOMH value is from NV memory VCOMH value is from the VCOMH[6:0] setting st -The nVM need be used in 1 parameter of VMCTR1 (C5h) - When nVM=0, the value of VMH[6:0] is from NV memory. So it must program the NV memory first. - When nVM=1, the vaule of VMH[6:0] is from $C5 register. It can fine-tune the display performance to the best quality by setting this register, and program this optium value to NV memory. -If this register not using the register need be reserved. Restriction -The deviation value of VCOMH between with Measurement and Specification: Max <=25mV -The deviation value of VCOMAC between with Measurement and Specification: Max <=50mV (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 100 Description re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status nVM Default Power On Sequence S/W Reset H/W Reset 0d 0d 0d Default Value LCM = `11' VMH[6:0] 40d 40d 40d LCM = `01' VMH[6:0] 26d 26d 26d --------------VMCTR1 (C5h) m nd .co re 101 Legend Command Parameter Display Flow Chart 1st Parameter: VMH[6:0] Action Mode Sequential transfer . (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.14. VMCTR2 (C6H): VCOM Control 2 C6H Inst / Para VMCTR2 st VMCTR2 (VCOM Control 2) D/CX 0 WRX RDX 1 D17-8 D7 1 0 D6 1 0 D5 0 VMA5 D4 0 VMA4 D3 0 VMA3 D2 1 VMA2 D1 1 VMA1 D0 0 VMA0 (Code) (C6H) 1 Parameter 1 1 NOTE: "-" Don't care, can be set to VDDI or DGND level -Set VCOMAC Voltage VMA[5:0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VCOMAC 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400 4.450 4.500 4.550 4.600 4.650 4.700 4.750 VMA[5:0] 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VCOMAC 4.800 4.850 4.900 4.950 5.000 5.050 5.100 5.150 5.200 5.250 5.300 5.350 5.400 5.450 5.500 5.550 VMA[5:0] 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 111111 32 33 34 35 36 37 38 39 40 41 | 63 VCOMAC 5.600 5.650 5.700 5.750 5.800 5.850 5.900 5.950 6.000 Not Permitted Description Restriction -If this register not use the register need be reserved. -The deviation value of VCOMAC between with Measurement and Specification: Max <=50mV Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status LCM = `01' TM LC Type VMA[5:0] 21d 21d 21d w w w .m bt 102 re nd .co Default Value Default Power On Sequence S/W Reset H/W Reset (c) ORISE Technology Co., Ltd. Proprietary & Confidential m LCM = `11' ECB LC type VMA[5:0] 21d 21d 21d Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B --------------VMCTR2 (C6H) Legend Command Parameter Display Flow Chart Action 1 Parameter: VMA[5:0] st Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 103 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.15. RDVMOF (C8H): Read the VCOM Offset Value NV memory C8H Inst / Para RDVMOF st RDVMOF (Read the VCOM Offset Value NV memory) D/CX 0 WRX RDX 1 D17-8 D7 1 D6 1 D5 0 D4 0 D3 1 D2 0 D1 0 D0 0 (Code) (C8H) - 1 Parameter 0 1 nd 2 Parameter 1 1 nVM NOTE: "-" Don't care, can be set to VDDI or DGND level RVMF6 RVMF5 RVMF4 RVMF3 RVMF2 RVMF1 RVMF0 -Read the VCOM offset value from NV memory -The 1 parameter is dummy data. Description -The 2 parameter is VMF[6:0] value from NV memory or default value. nd st Restriction -If this register not use the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability Default w w .m Status Power On Sequence S/W Reset H/W Reset bt re nd .co 104 m Availability Yes Yes Yes Yes Yes Default Value- Legend w Serial I/F Mode RDVMOF (BEH) Parallel I/F Mode RDVMOF (BEH) Host Driver Command Parameter Display Flow Chart Send VMF[5:0] Dummy Read Action Mode Send VMF[5:0] Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.16. WRID2 (D1h): Write ID2 Value D0H Inst / Para WRID2 1 Parameter NOTE: "-" Don't care st WRID2 (Write ID2 Value) D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 1 D6 1 ID26 D5 0 ID25 D4 1 ID24 D3 0 ID23 D2 0 ID22 D1 0 ID21 D0 1 ID20 (Code) (D1h) - -Write 7-bits data of LCD module version to save it to NV memory. Description -The 1 parameter ID2[6:0] is LCD Module version ID. st Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability Default --------------- .m bt Status Power On Sequence S/W Reset H/W Reset re nd .co 105 m Availability Yes Yes Yes Yes Yes Default Value Not Fixed Not Fixed Not Fixed Legend Command w w WRID2 (D1h) Parameter Display Flow Chart w 1st Parameter: ID2[6:0] Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.17. WRID3 (D2h): Write ID3 Value D0H Inst / Para WRID3 1 Parameter NOTE: "-" Don't care st WRID3 (Write ID3 Value) D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 ID37 D6 1 ID36 D5 0 ID35 D4 1 ID34 D3 0 ID33 D2 0 ID32 D1 1 ID31 D0 0 ID30 (Code) (D2h) -Write 8-bits data of project code module to save it to NV memory. -The 1 parameter ID3[7:0] is product project ID. Description st Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability Default w --------------- .m Status Power On Sequence S/W Reset H/W Reset re bt nd .co 106 m Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h Legend Command w w WRID3 (D2h) Parameter Display Flow Chart 1st Parameter: ID3[7:0] Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.18. RDID4 (D3h): Read the ID4 value D4H Inst / Para RDID4 1 Parameter 2 Parameter 3 Parameter th 4 Parameter th 5 Parameter NOTE: "-" Don't care rd nd st RDID4 (Read the ID4 value) D/CX 0 1 1 1 1 1 WRX 1 1 1 1 1 RDX 1 D17-8 D7 1 ID417 ID427 ID437 ID447 D6 1 ID416 ID426 ID436 ID446 D5 0 ID415 ID425 ID435 ID445 D4 1 ID414 ID424 ID434 ID444 D3 0 ID413 ID423 ID433 ID443 D2 0 ID412 ID422 ID432 ID442 D1 1 ID411 ID421 ID431 ID441 D0 1 ID410 ID420 ID430 ID440 (Code) (D3h) -Read the Driver IC information from mask value. -The 2 parameter ID41[7:0] is Driver IC ID code. -ID41[7:0] is 06H. rd th th nd Description -The 3 parameter ID42[7:0] is Driver IC Part number ID. It is 16H. -The 4 & 5 parameter ID43[7:0] & ID44[7:0] are Driver IC version ID. Status Default w w .m Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In re Restriction - bt Power On Sequence S/W Reset H/W Reset ID41[7:0] 06H 06H 06H nd .co Availability Yes Yes Yes Yes Yes Default ValueID42[7:0] ID43[7:0] 14H 00H 14H 00H 14H 00H ID44[7:0] 00H 00H 00H w Serial I/F Mode RDID4 (D3h) Partial I/F Mode RDID4 (D3h) Host Driver m Legend Command -The 1 parameter is dummy data. st Parameter Display Dummy Clock Flow Chart Send ID41[7:0] Dummy Read Send ID41[7:0] Action Mode Send ID42[7:0] Send ID42[7:0] Sequential transfer Send ID43[7:0] Send ID43[7:0] (c) ORISE Technology Co., Ltd. Proprietary & Confidential 107 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.19. NVFCTR1 (D9h): NV Memory Function Controller 1 D9H Inst / Para NVFCTR1 1 Parameter NOTE: "-" Don't care1 st NVFCTR1 (NV Memory Function Controller 1) D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 0 D0 1 (Code) (D9h) - WVMH WVMH WVMH WVMH WVMH WVMH WVMH WVMH 7 6 5 4 3 2 1 0 - Write WVMH[6:0] for VCOMH voltage to $D9 when the value is considered as the optimum for display quality. - The endurence for SPFD54126B NV memory is 4 times for VCOMH, ID1, ID2 and ID3. START EXTC=VDDI SLPOUT($11) Check the display quality .m w bt VMCTR1($C5) = 8'b1xxx_xxxx DISPON($29) No w re w Description Yes Prepare the data that will be written into OTP cell OTP programming procedure RAMWR($2C) Optimum Display?? VMCTR1($C5) = 8'b0xxx_xxxx WRID1($D0) WRID2($D1) WRID3($D2) NVFCTR3($DF) 8'b1nnn_nnnn SLPIN($10) Wait more than 50ms Apply 7.75V at VGH pad Wait more than 200ms NVFCTR1 ($D9) Wait more than 500ms NVFCTR2 ($DE) Wait more than 10ms Remove external power from VGH pad Wait more than 10ms (c) ORISE Technology Co., Ltd. Proprietary & Confidential 108 nd .co The Optimum value for VCOMH = 7'bnnn_nnnn EXTC=VDDI --> Accessing Command2 enable m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Restriction The endurence of WVMH, ID1, ID2, and ID3 is 4 times. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Default Status Power On Sequence S/W Reset H/W Reset Default Value Not Fixed Not Fixed Not Fixed nd .co re 109 NVFCTR1 (D9h) m --------------- Legend Command Parameter Display Flow Chart st 1 Parameter: Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.20. NVFCTR2 (DEh): NV Memory Function Controller 2 DEH Inst / Para NVFCTR2 1 Parameter NOTE: "-" Don't care st NVFCTR2 (NV Memory Function Controller 2) D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 1 D6 1 D5 0 D4 1 D3 1 D2 1 D1 1 D0 0 (Code) (DEh) - Description - Please refer to $D9 for details. Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability Default --------------- .m bt Status Power On Sequence S/W Reset H/W Reset re nd .co 110 m Availability Yes Yes Yes Yes Yes Default Value Not Fixed Not Fixed Not Fixed Legend Command NVFCTR1 (DEh) w w Parameter Display Flow Chart w 1st Parameter: Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.21. NVFCTR3 (DFh): NV Memory Function Controller 3 DEH Inst / Para NVFCTR3 1 Parameter NOTE: "-" Don't care st NVFCTR3 (NV Memory Function Controller 3) D/CX 0 1 WRX RDX 1 1 D17-8 D7 1 1 D6 1 D5 0 D4 1 D3 1 D2 1 D1 1 D0 1 (Code) (DFh) - Description - Please refer to $D9 for details. Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability Default --------------- .m bt Status Power On Sequence S/W Reset H/W Reset re nd .co 111 m Availability Yes Yes Yes Yes Yes Default Value Not Fixed Not Fixed Not Fixed Legend Command NVFCTR3 (DFh) w w Parameter Display Flow Chart w 1st Parameter: Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.22. GMCTRP1 (E0H): Gamma (`+'polarity for Red color) Correction Characteristics Setting E0H Inst / Para GMCTRP1 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 Parameter 9 Parameter 10 Parameter 11 Parameter 12 Parameter 13 Parameter 14 Parameter 15 Parameter 16 Parameter NOTE: "-" Don't care th th th th th th th th th th th th th rd nd st GMCTRP1 (Gamma `+'polarity Correction Characteristics Setting) D/CX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WRX RDX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D17-8 - D7 1 - D6 1 - D5 1 R_PVR1 V1[5] R_PVR1 V2[5] R_PVR1 V61[5] R_PVR1 V62[5] - D4 0 R_PVR1 V0[4] R_PVR1 V1[4] R_PVR1 V2[4] R_PVR1 V61[4] R_PVR1 V62[4] R_PVR1 V63[4] R_PVR2 V13[4] R_PVR2 V50[4] - D3 0 R_PVR1 V0[3] R_PVR1 V1[3] R_PVR1 V2[3] R_PVR1 V61[3] R_PVR1 V62[3] R_PVR1 V63[3] R_PVR2 V13[3] R_PVR2 V50[3] R_PVR3 V4[3] R_PVR3 V8[3] R_PVR3 V20[3] R_PVR3 V27[3] R_PVR3 V36[3] R_PVR3 V43[3] R_PVR3 V55[3] R_PVR3 V59[3] D2 0 R_PVR1 V0[2] R_PVR1 V1[2] R_PVR1 V2[2] R_PVR1 V61[2] R_PVR1 V62[2] R_PVR1 V63[2] R_PVR2 V13[2] R_PVR2 V50[2] R_PVR3 V4[2] R_PVR3 V8[2] R_PVR3 V20[2] R_PVR3 V27[2] R_PVR3 V36[2] R_PVR3 V43[2] R_PVR3 V55[2] R_PVR3 V59[2] D1 0 R_PVR1 V0[1] R_PVR1 V1[1] R_PVR1 V2[1] R_PVR1 V61[1] R_PVR1 V62[1] R_PVR1 V63[1] R_PVR2 V13[1] R_PVR2 V50[1] R_PVR3 V4[1] R_PVR3 V8[1] R_PVR3 V20[1] R_PVR3 V27[1] R_PVR3 V36[1] R_PVR3 V43[1] R_PVR3 V55[1] R_PVR3 V59[1] D0 0 R_PVR1 V0[0] R_PVR1 V1[0] R_PVR1 V2[0] R_PVR1 V61[0] R_PVR1 V62[0] R_PVR1 V63[0] R_PVR2 V13[0] R_PVR2 V50[0] R_PVR3 V4[0] R_PVR3 V8[0] R_PVR3 V20[0] R_PVR3 V27[0] R_PVR3 V36[0] R_PVR3 V43[0] R_PVR3 V55[0] R_PVR3 V59[0] (Code) (E0h) -When turn ON the separate RGB gamma function the command is used for R gamma (`+'polarity) of GC0 correction characteristics setting Description -When turn OFF the separate RGB gamma function the command is used for gamma (`+' polarity) correction characteristics setting Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w w .m bt 112 re Default Status Power On Sequence S/W Reset H/W Reset (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co m Availability Yes Yes Yes Yes Yes Default Value ---------- Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B --------------GMCTRP1 (E0H) Legend Command Parameter 1st ~ 5th Parameter: V0RP [3:0] ~ V9 RP [3:0] Display Flow Chart Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 113 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.23. GMCTRN1 (E1H): Gamma (`-'polarity for Red color) Correction Characteristics Setting E1H Inst / Para GMCTRP1 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 Parameter 9 Parameter 10 Parameter 11 Parameter 12 Parameter 13 Parameter 14 Parameter 15 Parameter 16 Parameter NOTE: "-" Don't care th th th th th th th th th th th th th rd nd st GMCTRP1 (Gamma `+'polarity Correction Characteristics Setting) D/CX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WRX RDX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D17-8 - D7 1 - D6 1 - D5 1 R_NVR1 V1[5] R_NVR1 V2[5] R_NVR1 V61[5] R_NVR1 V62[5] - D4 0 R_NVR1 V0[4] R_NVR1 V1[4] R_NVR1 V2[4] R_NVR1 V61[4] R_NVR1 V62[4] R_NVR1 V63[4] R_NVR2 V13[4] R_NVR2 V50[4] - D3 0 R_NVR1 V0[3] R_NVR1 V1[3] R_NVR1 V2[3] R_NVR1 V61[3] R_NVR1 V62[3] R_NVR1 V63[3] R_NVR2 V13[3] R_NVR2 V50[3] R_NVR3 V4[3] R_NVR3 V8[3] R_NVR3 V20[3] R_NVR3 V27[3] R_NVR3 V36[3] R_NVR3 V43[3] R_NVR3 V55[3] R_NVR3 V59[3] D2 0 R_NVR1 V0[2] R_NVR1 V1[2] R_NVR1 V2[2] R_NVR1 V61[2] R_NVR1 V62[2] R_NVR1 V63[2] R_NVR2 V13[2] R_NVR2 V50[2] R_NVR3 V4[2] R_NVR3 V8[2] R_NVR3 V20[2] R_NVR3 V27[2] R_NVR3 V36[2] R_NVR3 V43[2] R_NVR3 V55[2] R_NVR3 V59[2] D1 0 R_NVR1 V0[1] R_NVR1 V1[1] R_NVR1 V2[1] R_NVR1 V61[1] R_NVR1 V62[1] R_NVR1 V63[1] R_NVR2 V13[1] R_NVR2 V50[1] R_NVR3 V4[1] R_NVR3 V8[1] R_NVR3 V20[1] R_NVR3 V27[1] R_NVR3 V36[1] R_NVR3 V43[1] R_NVR3 V55[1] R_NVR3 V59[1] D0 0 R_NVR1 V0[0] R_NVR1 V1[0] R_NVR1 V2[0] R_NVR1 V61[0] R_NVR1 V62[0] R_NVR1 V63[0] R_NVR2 V13[0] R_NVR2 V50[0] R_NVR3 V4[0] R_NVR3 V8[0] R_NVR3 V20[0] R_NVR3 V27[0] R_NVR3 V36[0] R_NVR3 V43[0] R_NVR3 V55[0] R_NVR3 V59[0] (Code) (E1h) -When turn OFF the separate RGB gamma function the command is used for gamma (`-' polarity) correction characteristics setting Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w Description w -When turn ON the separate RGB gamma function the command is used for R gamma (`-' polarity) of GC0 correction characteristics setting .m bt 114 re Default Status Power On Sequence S/W Reset H/W Reset (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co m Availability Yes Yes Yes Yes Yes Default Value ---------- Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B --------------GMCTRN1 (E1H) Legend Command Parameter 1st ~ 5th Parameter: V0RN [3:0] ~ V9 RN [3:0] Display Flow Chart Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 115 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.24. GMCTRP2 (E2H): Gamma (`+'polarity) for Green color Correction Characteristics Setting E2H Inst / Para GMCTRP1 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 Parameter 9 Parameter 10 Parameter 11 Parameter 12 Parameter 13 Parameter 14 Parameter 15 Parameter 16 Parameter NOTE: "-" Don't care th th th th th th th th th th th th th rd nd st GMCTRP1 (Gamma `+'polarity Correction Characteristics Setting) D/CX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WRX RDX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D17-8 - D7 1 - D6 1 - D5 1 G_PVR1 V1[5] G_PVR1 V2[5] G_PVR1 V61[5] G_PVR1 V62[5] - D4 0 G_PVR1 V0[4] G_PVR1 V1[4] G_PVR1 V2[4] G_PVR1 V61[4] G_PVR1 V62[4] G_PVR1 V63[4] G_PVR2 V13[4] G_PVR2 V50[4] - D3 0 G_PVR1 V0[3] G_PVR1 V1[3] G_PVR1 V2[3] G_PVR1 V61[3] G_PVR1 V62[3] G_PVR1 V63[3] G_PVR2 V13[3] G_PVR2 V50[3] G_PVR3 V4[3] G_PVR3 V8[3] G_PVR3 V20[3] G_PVR3 V27[3] G_PVR3 V36[3] G_PVR3 V43[3] G_PVR3 V55[3] G_PVR3 V59[3] D2 0 G_PVR1 V0[2] G_PVR1 V1[2] G_PVR1 V2[2] G_PVR1 V61[2] G_PVR1 V62[2] G_PVR1 V63[2] G_PVR2 V13[2] G_PVR2 V50[2] G_PVR3 V4[2] G_PVR3 V8[2] G_PVR3 V20[2] G_PVR3 V27[2] G_PVR3 V36[2] G_PVR3 V43[2] G_PVR3 V55[2] G_PVR3 V59[2] D1 0 G_PVR1 V0[1] G_PVR1 V1[1] G_PVR1 V2[1] G_PVR1 V61[1] G_PVR1 V62[1] G_PVR1 V63[1] G_PVR2 V13[1] G_PVR2 V50[1] G_PVR3 V4[1] G_PVR3 V8[1] G_PVR3 V20[1] G_PVR3 V27[1] G_PVR3 V36[1] G_PVR3 V43[1] G_PVR3 V55[1] G_PVR3 V59[1] D0 0 G_PVR1 V0[0] G_PVR1 V1[0] G_PVR1 V2[0] G_PVR1 V61[0] G_PVR1 V62[0] G_PVR1 V63[0] G_PVR2 V13[0] G_PVR2 V50[0] G_PVR3 V4[0] G_PVR3 V8[0] G_PVR3 V20[0] G_PVR3 V27[0] G_PVR3 V36[0] G_PVR3 V43[0] G_PVR3 V55[0] G_PVR3 V59[0] (Code) (E2h) Description Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w -When turn OFF the separate RGB gamma function the command is not used. w -When turn ON the separate RGB gamma function the command is only used for G gamma (`+'polarity) of GC0 correction characteristics setting .m bt 116 re Default Status Power On Sequence S/W Reset H/W Reset (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co m Availability Yes Yes Yes Yes Yes Default Value ---------- Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B --------------GMCTRP2 (E2H) Legend Command Parameter 1st ~ 5th Parameter: V0GP [3:0] ~ V9 GP [3:0] Display Flow Chart Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 117 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.25. GMCTRN2 (E3H): Gamma (`-'polarity) for Green color Correction Characteristics Setting E3H Inst / Para GMCTRP1 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 Parameter 9 Parameter 10 Parameter 11 Parameter 12 Parameter 13 Parameter 14 Parameter 15 Parameter 16 Parameter NOTE: "-" Don't care th th th th th th th th th th th th th rd nd st GMCTRP1 (Gamma `+'polarity Correction Characteristics Setting) D/CX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WRX RDX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D17-8 - D7 1 - D6 1 - D5 1 G_NVR1 V1[5] G_NVR1 V2[5] G_NVR1 V61[5] G_NVR1 V62[5] - D4 0 G_NVR1 V0[4] G_NVR1 V1[4] G_NVR1 V2[4] G_NVR1 V61[4] G_NVR1 V62[4] G_NVR1 V63[4] G_NVR2 V13[4] G_NVR2 V50[4] - D3 0 G_NVR1 V0[3] G_NVR1 V1[3] G_NVR1 V2[3] G_NVR1 V61[3] G_NVR1 V62[3] G_NVR1 V63[3] G_NVR2 V13[3] G_NVR2 V50[3] G_NVR3 V4[3] G_NVR3 V8[3] G_NVR3 V20[3] G_NVR3 V27[3] G_NVR3 V36[3] G_NVR3 V43[3] G_NVR3 V55[3] G_NVR3 V59[3] D2 0 G_NVR1 V0[2] G_NVR1 V1[2] G_NVR1 V2[2] G_NVR1 V61[2] G_NVR1 V62[2] G_NVR1 V63[2] G_NVR2 V13[2] G_NVR2 V50[2] G_NVR3 V4[2] G_NVR3 V8[2] G_NVR3 V20[2] G_NVR3 V27[2] G_NVR3 V36[2] G_NVR3 V43[2] G_NVR3 V55[2] G_NVR3 V59[2] D1 0 G_NVR1 V0[1] G_NVR1 V1[1] G_NVR1 V2[1] G_NVR1 V61[1] G_NVR1 V62[1] G_NVR1 V63[1] G_NVR2 V13[1] G_NVR2 V50[1] G_NVR3 V4[1] G_NVR3 V8[1] G_NVR3 V20[1] G_NVR3 V27[1] G_NVR3 V36[1] G_NVR3 V43[1] G_NVR3 V55[1] G_NVR3 V59[1] D0 0 G_NVR1 V0[0] G_NVR1 V1[0] G_NVR1 V2[0] G_NVR1 V61[0] G_NVR1 V62[0] G_NVR1 V63[0] G_NVR2 V13[0] G_NVR2 V50[0] G_NVR3 V4[0] G_NVR3 V8[0] G_NVR3 V20[0] G_NVR3 V27[0] G_NVR3 V36[0] G_NVR3 V43[0] G_NVR3 V55[0] G_NVR3 V59[0] (Code) (E3h) -When turn OFF the separate RGB gamma function the command is not used. Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w Description w -When turn ON the separate RGB gamma function the command is only used for G gamma (`-' polarity) of GC0 correction characteristics setting .m bt 118 re Default Status Power On Sequence S/W Reset H/W Reset (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co m Availability Yes Yes Yes Yes Yes Default Value ---------- Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B --------------GMCTRN2 (E3H) Legend Command Parameter 1st ~ 5th Parameter: V0GN [3:0] ~ V9 GN [3:0] Display Flow Chart Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 119 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.26. GMCTRP3 (E4H): Gamma (`+'polarity) for Blue color correction Characteristics Setting E4H Inst / Para GMCTRP1 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 Parameter 9 Parameter 10 Parameter 11 Parameter 12 Parameter 13 Parameter 14 Parameter 15 Parameter 16 Parameter NOTE: "-" Don't care th th th th th th th th th th th th th rd nd st GMCTRP1 (Gamma `+'polarity Correction Characteristics Setting) D/CX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WRX RDX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D17-8 - D7 1 - D6 1 - D5 1 B_PVR1 V1[5] B_PVR1 V2[5] B_PVR1 V61[5] B_PVR1 V62[5] - D4 0 B_PVR1 V0[4] B_PVR1 V1[4] B_PVR1 V2[4] B_PVR1 V61[4] B_PVR1 V62[4] B_PVR1 V63[4] B_PVR2 V13[4] B_PVR2 V50[4] - D3 0 B_PVR1 V0[3] B_PVR1 V1[3] B_PVR1 V2[3] B_PVR1 V61[3] B_PVR1 V62[3] B_PVR1 V63[3] B_PVR2 V13[3] B_PVR2 V50[3] B_PVR3 V4[3] B_PVR3 V8[3] B_PVR3 V20[3] B_PVR3 V27[3] B_PVR3 V36[3] B_PVR3 V43[3] B_PVR3 V55[3] B_PVR3 V59[3] D2 0 B_PVR1 V0[2] B_PVR1 V1[2] B_PVR1 V2[2] B_PVR1 V61[2] B_PVR1 V62[2] B_PVR1 V63[2] B_PVR2 V13[2] B_PVR2 V50[2] B_PVR3 V4[2] B_PVR3 V8[2] B_PVR3 V20[2] B_PVR3 V27[2] B_PVR3 V36[2] B_PVR3 V43[2] B_PVR3 V55[2] B_PVR3 V59[2] D1 0 B_PVR1 V0[1] B_PVR1 V1[1] B_PVR1 V2[1] B_PVR1 V61[1] B_PVR1 V62[1] B_PVR1 V63[1] B_PVR2 V13[1] B_PVR2 V50[1] B_PVR3 V4[1] B_PVR3 V8[1] B_PVR3 V20[1] B_PVR3 V27[1] B_PVR3 V36[1] B_PVR3 V43[1] B_PVR3 V55[1] B_PVR3 V59[1] D0 0 B_PVR1 V0[0] B_PVR1 V1[0] B_PVR1 V2[0] B_PVR1 V61[0] B_PVR1 V62[0] B_PVR1 V63[0] B_PVR2 V13[0] B_PVR2 V50[0] B_PVR3 V4[0] B_PVR3 V8[0] B_PVR3 V20[0] B_PVR3 V27[0] B_PVR3 V36[0] B_PVR3 V43[0] B_PVR3 V55[0] B_PVR3 V59[0] (Code) (E4h) Description -When turn OFF the separate RGB gamma function the command is not used. Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w -When turn ON the separate RGB gamma function the command is only used for B gamma (`+'polarity) of GC0 correction characteristics setting w .m Availability Yes Yes Yes Yes Yes Status Power On Sequence S/W Reset H/W Reset Default Value ---------120 Default (c) ORISE Technology Co., Ltd. Proprietary & Confidential bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B --------------GMCTRP3 (E4H) Legend Command Parameter 1st ~ 5th Parameter: V0BP [3:0] ~ V9 BP [3:0] Display Flow Chart Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 121 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.27. GMCTRN3 (E5H): Gamma (`-'polarity) for Blue color Correction Characteristics Setting E5H Inst / Para GMCTRP1 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter 6 Parameter 7 Parameter 8 Parameter 9 Parameter 10 Parameter 11 Parameter 12 Parameter 13 Parameter 14 Parameter 15 Parameter 16 Parameter NOTE: "-" Don't care th th th th th th th th th th th th th rd nd st GMCTRP1 (Gamma `+'polarity Correction Characteristics Setting) D/CX 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WRX RDX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D17-8 - D7 1 - D6 1 - D5 1 B_NVR1 V1[5] B_NVR1 V2[5] B_NVR1 V61[5] B_NVR1 V62[5] - D4 0 B_NVR1 V0[4] B_NVR1 V1[4] B_NVR1 V2[4] B_NVR1 V61[4] B_NVR1 V62[4] B_NVR1 V63[4] B_NVR2 V13[4] B_NVR2 V50[4] - D3 0 B_NVR1 V0[3] B_NVR1 V1[3] B_NVR1 V2[3] B_NVR1 V61[3] B_NVR1 V62[3] B_NVR1 V63[3] B_NVR2 V13[3] B_NVR2 V50[3] B_NVR3 V4[3] B_NVR3 V8[3] B_NVR3 V20[3] B_NVR3 V27[3] B_NVR3 V36[3] B_NVR3 V43[3] B_NVR3 V55[3] B_NVR3 V59[3] D2 0 B_NVR1 V0[2] B_NVR1 V1[2] B_NVR1 V2[2] B_NVR1 V61[2] B_NVR1 V62[2] B_NVR1 V63[2] B_NVR2 V13[2] B_NVR2 V50[2] B_NVR3 V4[2] B_NVR3 V8[2] B_NVR3 V20[2] B_NVR3 V27[2] B_NVR3 V36[2] B_NVR3 V43[2] B_NVR3 V55[2] B_NVR3 V59[2] D1 0 B_NVR1 V0[1] B_NVR1 V1[1] B_NVR1 V2[1] B_NVR1 V61[1] B_NVR1 V62[1] B_NVR1 V63[1] B_NVR2 V13[1] B_NVR2 V50[1] B_NVR3 V4[1] B_NVR3 V8[1] B_NVR3 V20[1] B_NVR3 V27[1] B_NVR3 V36[1] B_NVR3 V43[1] B_NVR3 V55[1] B_NVR3 V59[1] D0 0 B_NVR1 V0[0] B_NVR1 V1[0] B_NVR1 V2[0] B_NVR1 V61[0] B_NVR1 V62[0] B_NVR1 V63[0] B_NVR2 V13[0] B_NVR2 V50[0] B_NVR3 V4[0] B_NVR3 V8[0] B_NVR3 V20[0] B_NVR3 V27[0] B_NVR3 V36[0] B_NVR3 V43[0] B_NVR3 V55[0] B_NVR3 V59[0] (Code) (E5h) Description -When turn OFF the separate RGB gamma function the command is not used. Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w -When turn ON the separate RGB gamma function the command is only used for B gamma (`-' polarity) of GC0 correction characteristics setting w .m Availability Yes Yes Yes Yes Yes Status Power On Sequence S/W Reset H/W Reset Default Value ---------122 Default (c) ORISE Technology Co., Ltd. Proprietary & Confidential bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B --------------GMCTRN3 (E5H) Legend Command Parameter 1st ~ 5th Parameter: V0BN [3:0] ~ V9 BN [3:0] Display Flow Chart Action Mode Sequential transfer (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 123 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7. FUNCTION DESCRIPTION 7.1. MCU & RGB Interface The SPFD54126B features System interfaces and RGB interface to satisfy various needs of small or medium size's LCD panel. Based on the application requirements, there are two display modes mostly used in the LCD end product. 1. Still picture display mode 2. Moving picture display mode. System interface is suitable for still picture display while RGB interface are suitable for moving picture display. Table 6.1 summarizes different interfaces for various display requirements. Table 7.1 MCU & RGB Interface Comparisons table Function "00" Mode selection 1 IM2='1' 8080/ 6800 IF Motion or Still D[B:0] CSX Input signal GRAM Write cycle GRAM Read Cycle Command setting VSYNC I/F TE Function Normal / Partial mode Idle Mode (IDM H/W pin) Display On/ Off -By command setting (SHUT H/W pin) -Don't care in this mode, but should be set to VDDI or DGND. Data inverter (REV H/W pin) WRX (R/WX), RDX (E) Refer WRX 8080/ 6800 IF + SPI I/F MCU Mode 1 Mode selection 2 Motion /Still selection Input data IM2='0' SPI I/F Still D0 = SDA D/CX = SCL CSX Refer SCL MCU Mode 2 IM2='1' 8080/ 6800 IF Motion or Still D[B:0] CSX WRX (R/WX), RDX (E) Refer WRX IM2='0' SPI I/F Still RCM1, RCM0 RCM1, RCM0 "01" "10" "11" RGB I/F + SPI I/F RGB Mode 2 ICM='0' ICM='1' RGB-2 I/F + SPI I/F Motion or Stil D[B:0] PCLK VS, HS, DE Still SDA H/W pin D/CX = SCL CSX nd .co ICM='0' Motion or Still D[B:0] PCLK VS, HS, DE Refer PCLK RGB Mode 1 ICM='1' RGB-1 I/F + SPI I/F Still SCL H/W pin re SPI_CSX Refer SCL SDA H/W pin bt SMX, SMY, SRGB -When Power On or H/W reset, those function follow H/W pins setting first. w w D[7:0] D0 = SDA w Refer Internal Oscillator .m Refer SCL Refer PCLK Refer SCL Refer Refer Refer Refer PCLK Internal Refer PCLK Internal Internal Oscillator Oscillator Oscillator D[7:0] SDA H/W pin SDA SDA H/W pin SDA SDA H/W pin -No support this function in these modes -By command setting -By command setting -By IDM H/W pin -IDM On/OFF (39H/28H) are disable -By SHUT H/W pin -SLPIN(10H), SLPOUT(11H), Display On/OFF (29h/28H) are disable -By REV H/W pin -INVON/OFF (21H/20H) are disable -By command setting -Default is OFF -By command setting -By command setting -Default is ON DE H/W pin -Don't care in this mode, but should be set to VDDI or DGND RL H/W pin TB H/W pin Blanking porch Colors Format -Don't care in this mode -Control by IFPF[2:0] of COLMOD(3AH) -The data latched by rising edge of PCLK when DE='1' -When DE='0' area, output is -When display data coming blanking display the DE signal should be VDDI level -Don't care in this mode, but -By H/W pin should be set to VDDI or -No commands conflict DGND -Control by RGBBPCTR -Control by DE signal (D5) -Control by VIPF[3:0] of COLMOD (3AH) Note 1: RCM1 and RCM0 are H/W setting pins. Note 2: In RGB + SPI I/F (RCM="1x"), VS, HS, DE, PCLK and D[17:0] are Hi-Z by Driver and can be stop for Host, when ICM='1'. Note 3: In RGB + SPI I/F (RCM="1x"), the data deliver via GRAM (c) ORISE Technology Co., Ltd. Proprietary & Confidential 124 Apr. 25, 2006 Preliminary Version: 0.1 m SDA H/W pin D/CX = SCL CSX Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Note 4: When Power on Driver IC should be detect SMX, SMY, SRGB H/W setting Note 5: When Power on Driver IC should be detect RCM1, RCM0 H/W setting and get into the I/F mode. Note 6: When Power on Driver IC should be detect LCM1, LCM0 H/W setting and get into the setting mode. Note 7: When Power on Driver IC should be detect GM1, GM0 H/W setting and get into the setting mode. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 125 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2. MPU Interface 7.2.1. Interface Type Selection The MPU interfaces of SPFD54126B support 8-bit, 9-bit, 16-bit, and 18-bit's 80- or 68-system Interface and Serial Peripheral Interface (SPI), which can be set by the P68 and IM2/1/0 pins. The MPU interface can set instructions and access RAM. Table 6.2.1 depicts the interface corresponding to P68and IM2/1/0 settings. Table 7.2.1 P68 IM2 0 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 7.2.2. 8080-Series Parallel interface(P68='0') Table 7.2.2 The function of 8080-series parallel interface P68 IM2 0 1 IM1 0 IM0 0 Interface 8-bits Parallel D/CX 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 RDX 1 1 1 1 1 1 1 1 WRX 1 1 1 1 1 1 1 1 Function Write 8-bits command (D7 to D0) Write 8-bits display data or 8-bits parameter (D7 to D0) Read 8-bits command (D7 to D0) Read 8-bits parameter or status (D7 to D0) Write 8-bits command (D7 to D0) Write 16-bits display data (D15 to D0) or 8-bits parameter (D7 to D0) Read 8-bits command (D7 to D0) Read 8-bits parameter or status (D7 to D0) Write 8-bits command (D7 to D0) Write 9-bits display data (D8 to D0) or 8-bits parameter (D7 to D0) Read 8-bits command (D7 to D0) Read 8-bits parameter or status (D7 to D0) Write 8-bits command (D7 to D0) Write 18-bits display data (D17 to D0) or 8-bits parameter (D7 to D0) Read 8-bits command (D7 to D0) Read 8-bits parameter or status (D7 to D0) 0 1 0 1 16-bits Parallel 0 1 1 0 9-bits Parallel 0 1 1 1 18-bits Parallel (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w The interface function of 8080-series parallel interface are given in Table 6.2.2 w The 8080-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is low state (DGND). Interface bus width can be selected with IM2, IM1 and IM0. .m The Graphics Controller Chip reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX='1', D[17:0] bits are display RAM data or command parameters. When D/C='0', D[17:0] bits are commands. bt 126 The MCU uses a 11-wires 8-data parallel interface or 19-wires 16-data parallel interface or 12-wires 9-data parallel interface or 21-wires 18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write, RDX is the parallel data read and D[17:0] is parallel data. re nd .co IM1 0 0 1 1 0 0 1 1 IM0 0 1 0 1 0 1 0 1 Interface 3-Pin Serial interface 8080 MCU 8-bits Parallel 8080 MCU 16-bits Parallel 8080 MCU 9-bits Parallel 8080 MCU 18-bits Parallel 3-Pin Serial interface 6800 MCU 8-bits Parallel 6800 MCU 16-bits Parallel 6800 MCU 9-bits Parallel 6800 MCU 18-bits Parallel Read back selection Via the read instruction (8-bits, 24-bits and 32-bits read parameter RDX strobe (8-bits read data and 8-bits read parameter) RDX strobe (16-bits read data and 8-bits read parameter) RDX strobe (9-bits read data and 8-bits read parameter) RDX strobe (18-bits read data and 8-bits read parameter) Via the read instruction (8-bits, 24-bits and 32-bits read parameter E strobe (8-bits read data and 8-bits read parameter) E strobe (16-bits read data and 8-bits read parameter) E strobe (9-bits read data and 8-bits read parameter) E strobe (18-bits read data and 8-bits read parameter) m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.2.1. Write cycle sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX high-low-high sequence) consists of 3 control (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (='0') and vice versa it is data (='1'). WRX D[17:0] Fig. 7.2.2.1.1 8080-Series WRX Protocol Note: WRX is an unsynchronized signal (It can be stopped) 1-byte command 2-byte command N-byte command (PA=N-1) D/CX RDX WRX D[17:0] Host [17:0] Host to LCD Driver [17:0] LCD to Host] S CMD `1' w CMD w CSX w RESX `1' PA1 .m D[17:0] S CMD CMD PA1 bt CMD re PA1 nd .co PAN-2 PAN-1 The host starts to control D[17:0] lines when there is a falling edge of the WRX The display writes D[17:0] lines when there is a falling edge of the WRX m P PAN-2 PAN-1 P PAN-2 PAN-1 P Signal on D[17:0], DCX. R/WX, E pins during CSX='1' are ignored The host stops to control D[17:0] lines CMD PA1 S CMD Hi-Z CMD PA1 CMD PA1 CMD: Write command code PA: Parameter or RAM data Fig. 7.2.2.1.2 8080-Series parallel bus protocol, Write to register or display RAM (c) ORISE Technology Co., Ltd. Proprietary & Confidential 127 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.2.2. Read Cycle Sequence The read cycle (RDX high-low-high sequence) means that the host reads information from display via interface. The display sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX. RDX D[17:0] Fig. 7.2.2.2.1 8080-Series RDX Protocol Note: RDX is an unsynchronized signal (It can be stopped) Read Parameter RESX CSX D/CX RDX WRX D[17:0] Host [17:0] Host to LCD Driver [17:0] LCD to Host] `1' S CMD w w DM w .m D[17:0] S CMD DM PA bt CMD re Read display RAM data nd .co DM data The display starts to control D[17:0] lines when there is a falling edge of the RDX The host reads D[17:0] lines when there is a rising edge of RDX The display stops to control D[17:0] m data P PA CMD DM data data P S CMD Hi-Z Hi-Z CMD Hi-Z Hi-Z P S DM PA DM data data P CMD: Write command code PA: Parameter or RAM data DM: Dummy Signal on D[17:0], DCX. R/WX, E pins during CSX='1' are ignored Fig. 7.2.2.2.2 8080-Series parallel bus protocol, Read data from register or display RAM (c) ORISE Technology Co., Ltd. Proprietary & Confidential 128 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.3. 6800-Series Parallel Interface (P68='1') The MCU uses a 11-wires 8-data parallel interface or 19-wires 16-data parallel interface or 12-wires 9-data parallel interface or 21-wires 18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. The R/WX is the Read/Write flag and D[17:0] is parallel data. The Graphics Controller Chip reads the data at the falling edge of E signal when R/WX='1' and Writes the data at the falling of the E signal when R/WX='0'. The D/CX is the data/command flag. When D/CX='1', D[17:0] bits are display RAM data or command parameters. When D/C='0', D[17:0] bits are commands. The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM1 and IM0. The interface functions of 6800-series parallel interface are given in Table 7.2.3. Table 7.2.3 The function of 6800-series parallel interface P68 IM2 IM1 IM0 1 1 0 0 Interface 8-bits Parallel D/CX 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 R/WX 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 E Function Write 8-bits command (D7 to D0) Write 8-bits display data or 8-bits parameter (D7 to D0) Read 8-bits command (D7 to D0) Read 8-bits parameter or status (D7 to D0) Write 8-bits command (D7 to D0) Write 16-bits display data (D15 to D0) or 8-bits parameter (D7 to D0) Read 8-bits command (D7 to D0) Read 8-bits parameter or status (D7 to D0) Write 8-bits command (D7 to D0) Write 9-bits display data (D8 to D0) or 8-bits parameter (D7 to D0) Read 8-bits command (D7 to D0) Read 8-bits parameter or status (D7 to D0) Write 8-bits command (D7 to D0) Write 18-bits display data (D17 to D0) or 8-bits parameter (D7 to D0) Read 8-bits command (D7 to D0) Read 8-bits parameter or status (D7 to D0) 1 1 0 1 16-bits Parallel 1 1 1 1 18-bits Parallel (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 129 1 1 1 0 9-bits Parallel re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.3.1. Write cycle sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (='0') and vice versa it is data (='1'). R/WX `0' E D[17:0] Fig. 7.2.3.1.1 6800-Series Write Protocol Note: E is an unsynchronized signal (It can be stopped) D[17:0] RESX CSX D/CX R/WX E D[17:0] `1' S CMD w CMD w 1-byte command 2-byte command .m PA1 bt N-byte command (PA=N-1) CMD re PA1 PAN-2 nd .co The host starts to control D[17:0] lines when there is a rising edge of the E The display writes D[17:0] lines when there is a falling edge of the E The host stops to control D[17:0] lines m PAN-1 P PAN-2 PAN-1 P PAN-2 PAN-1 P Signal on D[17:0], DCX. R/WX, E pins during CSX='1' are ignored `0' S CMD w CMD PA1 CMD PA1 Host [17:0] Host to LCD Driver [17:0] LCD to Host] S CMD Hi-Z CMD PA1 CMD PA1 CMD: Write command code PA: Parameter or RAM data Fig. 7.2.3.1.2 6800-Series parallel bus protocol, Write to register or display RAM (c) ORISE Technology Co., Ltd. Proprietary & Confidential 130 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.3.2. Read cycle sequence The read cycle means that the host reads information (command or/and data) to the display via the interface. Each read cycle (E low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (='0') and vice versa it is data (='1'). R/WX `1' E D[17:0] Fig. 7.2.3.2.1 6800-Series Read Protocol Note: E is an unsynchronized signal (It can be stopped) RESX CSX D/CX R/WX E D[17:0] Host [17:0] Host to LCD Driver [17:0] LCD to Host] `1' `0' S CMD w D[17:0] S CMD DM w Read Parameter w .m Read display RAM data PA bt CMD DM data re nd .co The display starts to control D[17:0] lines when there is a rising edge of the E The host reads D[17:0] lines when there is a falling edge of the E The display stops to control D[17:0] lines m data P data P P data P Signal on D[17:0], DCX. R/WX, E pins during CSX='1' are ignored `1' DM PA CMD DM data S CMD Hi-Z Hi-Z CMD Hi-Z Hi-Z S DM PA DM data CMD: Write command code PA: Parameter or RAM data DM: Dummy Fig. 7.2.3.2.2 6800-Series parallel bus protocol, Read data from register or display RAM (c) ORISE Technology Co., Ltd. Proprietary & Confidential 131 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.4. Serial Peripheral interface (SPI) The selection of this interface is done by IM2. See the Table 7.2.4. The serial interface is a 3-pin 9-bits bi-directional interface for communication between the micro controller and the LCD driver chip. The 3-pin serial use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary. Table 7.2.4 Serial Interface Type Selection P68 `-` IM2 0 IM1 `-` IM0 Interface `-` 3-Pin Serial interface Read back selection Via the read instruction (8-bits, 24-bits and 32-bits read parameter 7.2.4.1. Command Write Mode Any instruction can be sent in any order to the DRIVER. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission. 3-pin Serial Data Stream Format Transmission byte(TB) may be a command or a data D/CX (TB) D/CX .m bt (TB) MSB LSB D/CX D7 D6 D5 D4 D3 D2 D1 D0 re D/CX (TB) TB Fig. 7.2.4.1.1 Serial interface data Stream format When CSX is high, SCL clock is ignored. During the high time of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low. SDA is sampled at the rising edge of CSX. D/CX indicates, whether the byte is command code (D/CX='0') or parameter/RAM data (D/CX='1'). It is sampled when first rising edge of CSX. If CSX stay low after the last bit of command/data byte, the serial interface expects the D/CX bit of the next byte at the next rising edge of SCL. S w w w TB nd .co D/C m D3 D2 The write mode of the interface means the micro controller writes commands and data to the 3-Pin serial data packet contains a control bit D/CX and a transmission byte. If D/CX is low, the transmission byte is interpreted as command byte. If D/CX is high, the transmission byte is stored in the display data RAM (Memory write command), or command register as parameter. P CSX Host (MCU to Driver) SDA SCL 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D1 D0 Command Command / Parameter CSX can be `H' between parameter / command and parameter /command SCL and SDA during CSX='H' is i lid Fig. 7.2.4.1.2 Serial interface Write protocol (Write to register with control bit in transmission) (c) ORISE Technology Co., Ltd. Proprietary & Confidential 132 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.4.2. Read Functions The read mode of the interface means that the micro controller reads register value from the Driver. To do the micro controller first has to send a command (Read ID or register command) and then the following byte is transmitted in the opposite direction. After the read status command has been sent, the SDA lin must be set to tri-state no later than at the falling edge of SCL of the last bit. 3-Pin Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read) S TB TB P S CSX Host SCL SDA (SDI) D/CX D7 D6 D5 D4 D3 D2 D1 D0 High-Z m D2 D1 D0 D/CX Driver SDA (SDO) High-Z D7 D6 S TB re 3-Pin Serial Protocol (for RDDID command: 24-bit read) nd .co D5 D4 D3 TB P S CSX Host SCL SDA (SDI) D/CX D7 D6 D5 D4 D3 w .m D0 bt High-Z Driver w SDA (SDO) High-Z w D2 D1 D/CX D23 D22 D21 D20 D19 D3 D2 D1 D0 Dummy Clock Cycle 3-Pin Serial Protocol (for RDDST command: 32-bit read) S TB TB P S CSX Host SCL SDA (SDI) D/CX D7 D6 D5 D4 D3 D2 D1 D0 High-Z D/CX Driver SDA (SDO) High-Z D31 D30 D29 D28 D27 D3 D2 D1 D0 Dummy Clock Cycle Fig. 7.2.4.2.1 3-pin Serial interface Read protocol (c) ORISE Technology Co., Ltd. Proprietary & Confidential 133 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.5. Data Transfer Break and Recovery If there is a break in data transmission by RESX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been High state. See the following example S TB TB P CSX RESX SCL SDA Wait for more than 10s Host (MPU to Driver) D/CX D7 D6 D5 D4 D3 D2 nd .co D/CX D7 D6 m D5 D4 D3 D2 D1 D0 Command / Parameter / Data Command Fig. 7.2.5.1 Serial bus protocol, write mode - interrupted by RESX S w TB w w If there is a break in data transmission by CSX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example .m bt re SCL and SDA during RESX = "L" is invalid and next byte becomes command TB P CSX SCL Host (MPU to Driver) SDA D/CX D7 D6 D5 D4 D/CX D7 D6 D5 D4 D3 D2 D1 D0 Command / Parameter / Data Break Command / Parameter / Data Fig. 7.2. 5.2 Serial bus protocol, write mode - interrupted by CSX (c) ORISE Technology Co., Ltd. Proprietary & Confidential 134 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B If 1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below. Break PARA11 is sucessfully sended but PARA12 is breaked and need to be transfered again CMD1 PARA11 PARA12 CMD2 PARA11 PARA12 m CMD1 PARA13 Command1 with 1st parameter (PARA11) should be executed again to write remained parameter (PARA12 and PARA13) Fig.7.2.5.3 Write interrupts recovery (serial interface) Break w CMD1 w CMD1 w PARA11 .m CMD2 PARA11 is sucessfully sent but the other parameters are not sent and break happeds by the other command. bt 135 If a 2 or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value. re PARA11 nd .co PARA12 PARA13 Command1 with 1st parameter (PARA11) should be executed again to write remained parameter (PARA12 and PARA13) Fig. 7.2.5.4 Write interrupts recovery (both serial and parallel interface) (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.6. Data Transfer Pause It will be possible when transferring a Command, Frame Memory Data or Multiple Parameter Data to invoke a pause in the data transmission. If the Chip Select Line is released after a whole byte of a Frame Memory Data or Multiple Parameter Data has been completed, then DRIVER will wait and continue the Frame Memory Data or Parameter Data Transmission from the point where it was paused. If the Chip Select Line is released after a whole byte of a command has been completed, then the Display Module will receive either the command's parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter 7.2.6.1. Serial Interface Pause S TB nd .co m TB P CSX Host (MPU to Driver) SCL SDA D7 D6 D5 D4 D3 D2 .m bt D1 D0 D7 D6 D5 re Pause D/CX D/CX D4 D3 D2 D1 D0 Command / Parameter / Data w Command / Parameter / Data SCL and SDA during CSX = "H" is invalid 7.2.6.2. Parallel Interface Pause CSX D/CX RDX WRX D[17:0] D17 to D0 w Fig. 7.2.6.1 Serial interface Pause Protocol (pause by CSX) w Pause D17 to D0 Command / Parameter Pause Command / Parameter Fig. 7.2.6.2 Parallel bus Pause Protocol (paused by CSX) (c) ORISE Technology Co., Ltd. Proprietary & Confidential 136 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.2.7. Data Transfer Modes The Module has three kinds colour modes for transferring data to the display RAM. These are 12-bit colour per pixel, 16-bit colour per pixel and 18-bit colour per pixel. The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods. 7.2.7.1. Method 1 The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer is reset to the start point and the next Frame is written. Start Start Frame Memory Write Image Data Frame 1 Image Data Frame 2 Image Data Frame 3 Stop Any Command Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a new Frame is downloaded. Start Start Frame Memory Write Image Data Frame 1 Any Command re 137 Stop Note: 1) These apply to all data transfer Colour modes on both serial and parallel interfaces. 2) The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the frame memory. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w Any Command w .m bt Start Frame Memory Write nd .co 7.2.7.2. Method 2 Image Data Frame 2 m Any Command Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3. MCU Data Colour Coding 7.3.1. MCU Data Colour Coding for RAM data Write - Parallel 8-Bits Bus Interface (IM1, IM0= "00") Table 7.3.1.1 8-Bits Parallel Interface Set Table Register D17 D16 D15 D14 D13 D12 D11 D10 Command x x x x x x x x 3AH D17 D16 D15 D14 D13 D12 D11 D10 x x x x x x x x 03h x x x x x x x x x x x x x x x x x x x x x x x x 05h x x x x x x x x x x x x x x x x 06h x x x x x x x x x x x x x x x x D9 x D9 x x x x x x x x D8 x D8 x x x x x x x x D7 0 D7 R3 B3 G3 R4 G2 R5 G5 B5 D6 0 D6 R2 B2 G2 R3 G1 R4 G4 B4 D5 1 D5 R1 B1 G1 R2 G0 R3 G3 B3 D4 0 D4 R0 B0 G0 R1 B4 R2 G2 B2 D3 1 D3 G3 R3 B3 R0 B3 R1 G1 B1 D2 1 D2 G2 R2 B2 G5 B2 R0 G0 B0 D1 0 D1 G1 R1 B1 G4 B1 x x x D0 Command 0 2CH D0 Colour G0 4K-Colour R0 (2-pixels/ 3-byyes) B0 G3 65K-Colour B0 (1-pixels/ 2-byyes) x 262K-Colour x (1-pixels/ 3byyes) x - Parallel 16-Bits Bus Interface (IM1, IM0= "01") Table 7.3.1.2 16-Bits Parallel Interface Set Table Register D17 D16 D15 D14 D13 D12 D11 D10 D9 Command x x x x x x x x x 3AH D17 D16 D15 D14 D13 D12 D11 D10 D9 03h x x x x x x R3 R2 R1 05h x x R4 R3 R2 R1 R0 G5 G4 x x R5 R4 R3 R2 R1 R0 x 06h x x B5 B4 B3 B2 B1 B0 x x x G5 G4 G3 G2 G1 G0 x re D8 x D8 R0 G3 x x x D7 0 D7 G3 G2 G5 R5 B5 nd .co D6 0 D6 G2 G1 G4 R4 B4 D5 1 D5 G1 G0 G3 R3 B3 D4 0 D4 G0 B4 G2 R2 B2 m D4 0 D4 R1 B4 D4 0 D4 G0 B4 B4 - Parallel 9-Bits Bus Interface (IM1, IM0= "10") Table 7.3.1.3 9-Bits Parallel Interface Set Table Register D17 D16 D15 D14 D13 D12 D11 D10 Command x x x x x x x x 3AH D17 D16 D15 D14 D13 D12 D11 D10 x x x x x x x x 06h x x x x x x x x D9 x D9 x x D8 x D8 R5 G2 D7 0 D7 R4 G1 D6 0 D6 R3 G0 D5 1 D5 R2 B5 D3 1 D3 R0 B3 D2 1 D2 G5 B2 D1 0 D1 G4 B1 D0 0 D0 G3 B0 Register 2CH Colour 262K-Colour (1-pixels/ 2bytes) - Parallel 18-Bits Bus Interface (IM1, IM0= "11") Table 7.3.1.4 18-Bits Parallel Interface Set Table Register D17 D16 D15 D14 D13 D12 D11 D10 D9 Command x x x x x x x x x 3AH D17 D16 D15 D14 D13 D12 D11 D10 D9 03h x x x x x x R3 R2 R1 05h x x R4 R3 R2 R1 R0 G5 G4 06h R5 R4 R3 R2 R1 R0 G5 G4 G3 Note: `x' Don't care, but need to set VDDI or DGND level. w w D3 1 D3 B3 B3 G1 R1 B1 D2 1 D2 B2 B2 G0 R0 B0 D1 0 D1 B1 B1 x x x D0 0 D0 B0 B0 x x x w .m Command 2CH Colour 4K-Colour 65K-Colour 262K-Colour (2-pixels/ 3byyes) bt D8 x D8 R0 G3 G2 D7 0 D7 G3 G2 G1 D6 0 D6 G2 G1 G0 D5 1 D5 G1 G0 B5 D3 1 D3 B3 B3 B3 D2 1 D2 B2 B2 B2 D1 0 D1 B1 B1 B1 D0 0 D0 B0 B0 B0 Register 2CH Colour 4K-Colour 65K-Colour 262K-Colour (c) ORISE Technology Co., Ltd. Proprietary & Confidential 138 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.1.1. Parallel 8-Bits Bus Interface for RAM Data Write (IM1, IM0= "00") Different display data formats are available for three colours depth supported by listed below. - 4K-Colours, RGB 4,4,4-bits input data. (3AH="03h") - 65K-Colours, RGB 5,6,5-bits input data. (3AH="05h") - 262K-Colours, RGB 6,6,6-bits input data. (3AH="06h") (1). 8-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH="03h" There are 2 pixels (6 sub-pixels) per 3-bytes. IM1/IM0 CSX D/CX WRX RDX R/WX E D7 D6 D5 D4 D3 D2 D1 D0 `1' `0' IM1, IM0 = "00" re nd .co 8080-Series control pins 6800-Series control pins 0 0 1 0 1 1 0 0 w .m R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 bt G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 m R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 RESX `1' w w Pixel n 12-bits Pixel n+1 12-bits Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits) 18-bits 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 12-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 139 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B (2). 8-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH="05h" There are 1 pixels (3 sub-pixels) per 2-bytes. RESX IM1/IM0 CSX D/CX WRX RDX R/WX E D7 D6 D5 D4 D3 D2 D1 D0 `1' IM1, IM0 = "00" `1' `0' m nd .co re G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 8080-Series control pins 6800-Series control pins 0 0 1 0 1 1 0 0 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 w .m G1, Bit 5 G1, Bit 4 G1, Bit 3 bt 18-bits 140 G2, Bit 5 G2, Bit 4 G2, Bit 3 w w Pixel n 16-bits Pixel n+1 16-bits Look-Up Table for 4K-colors or data mapping (16-Bits to 18-Bits) 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.2-times transfer is used to transmit 1 pixel data with the 16-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B (3). 8-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH="06h" There are 1 pixels (3 sub-pixels) per 3-bytes. RESX IM1/IM0 CSX D/CX WRX RDX R/WX E D7 D6 D5 D4 D3 D2 D1 D0 `1' IM1, IM0 = "00" `1' `0' m nd .co R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 - 8080-Series control pins 6800-Series control pins re 0 0 1 0 1 1 0 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 - B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 - R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 - w w w .m bt Pixel n 18-bits Pixel n+1 18-bits R1 G1 B1 R2 G2 B2 R3 G3 B3 Frame Memory (c) ORISE Technology Co., Ltd. Proprietary & Confidential 141 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.1.2. Parallel 16-Bits Bus Interface for RAM Data Write (IM1, IM0="01") Different display data formats are available for three colors depth supported by listed below. - 4K-Colours, RGB 4,4,4-bits input data. (3AH="03h") - 65K-Colours, RGB 5,6,5-bits input data. (3AH="05h") - 262K-Colours, RGB 6,6,6-bits input data. (3AH="06h") (1). 16-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH="03h" There are 1 pixel (3 sub-pixels) per 1 bytes RESX `1' CSX D/CX WRX RDX `1' R/WX `0' E D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - bt R2 Bit 3 R2 Bit 2 R2 Bit 1 R2 Bit 0 G2 Bit 3 G2 Bit 2 G2 Bit 1 G2 Bit 0 B2 Bit 3 B2 Bit 2 B2 Bit 1 B2 Bit 0 re R3 Bit 3 R3 Bit 2 R3 Bit 1 R3 Bit 0 G3 Bit 3 G3 Bit 2 G3 Bit 1 G3 Bit 0 B3 Bit 3 B3 Bit 2 B3 Bit 1 B3 Bit 0 R4 Bit 3 R4 Bit 2 R4 Bit 1 R4 Bit 0 G4 Bit 3 G4 Bit 2 G4 Bit 1 G4 Bit 0 B4 Bit 3 B4 Bit 2 B4 Bit 1 B4 Bit 0 0 0 1 0 1 1 0 0 w w R1 Bit 3 R1 Bit 2 R1 Bit 1 R1 Bit 0 G1 Bit 3 G1 Bit 2 G1 Bit 1 G1 Bit 0 B1 Bit 3 B1 Bit 2 B1 Bit 1 B1 Bit 0 Pixel n 12-bits w .m Pixel n+1 12-bits Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits) 18-bits 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 12-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 142 nd .co Pixel n+2 m 8080-Series control 6800-Series control IM1/IM0 IM1 IM0="01" Pixel n+3 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B (2). 16-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH="05h" There are 1 pixel (3 sub-pixels) per 1 bytes RESX IM1/IM0 CSX D/CX WRX RDX R/WX E `1' IM1, IM0="01" `1' 8080-Series control pins D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D1 0 0 1 0 1 1 0 0 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 nd .co R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 m R3, Bi R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 `0' 6800-Series control pins R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 w w w .m G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n bt re Pixel n+1 Pixel n+2 Pixel n+3 16-bits 16-bits Look-Up Table for 4K-colors or data mapping (16-Bits to 18-Bits) 18-bits 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 143 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B (3). 16-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH="06h" There are 2 pixel (6 sub-pixels) per 3 bytes RESX IM1/IM0 CSX D/CX WRX RDX R/WX E D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 `1' IM1, IM0="01" `1' `0' 8080-Series control pins 6800-Series control pins 0 0 1 0 1 1 0 0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 - nd .co B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 - m G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 R3, Bit 5 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 - w Frame Memory w w .m G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 - Pixel n 18-bits bt 144 R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential re Pixel n+1 18-bits Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.1.3. Parallel 9-Bits Bus Interface for RAM Data Write (IM1, IM0="10") Different display data formats are available for three colors depth supported by listed below. - 262K-Colours, RGB 6,6,6-bits input data. (3AH="06h") (1). 9-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH="06h" There is 1 pixel (3 sub-pixels) per 2 bytes RESX IM1/IM0 CSX D/CX WRX RDX R/WX E `1' IM1, IM0 = "10" `1' `0' nd .co 0 0 1 0 1 1 0 0 m 8080-Series control pins 6800-Series control pins D8 D7 D6 D5 D4 D3 D2 D1 D0 .m R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 0 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 bt G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 re G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 w w w Pixel n 18-bits 18-bits Pixel n+1 Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 145 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.1.4. Parallel 18-Bits Bus Interface for RAM Data Write (IM1, IM0="11") Different display data formats are available for three colors depth supported by listed below. - 4K-Colours, RGB 4,4,4-bits input data. (3AH="03h") - 65K-Colours, RGB 5,6,5-bits input data. (3AH="05h") - 262K-Colours, RGB 6,6,6-bits input data. (3AH="06h") (1). 18-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH="03h" There is 1 pixel (3 sub-pixels) per 1 bytes RESX `1' IM1/IM0 IM1 IM0="11" D/CX WRX RDX `1' R/WX `0' E D17 D16 - re bt R2 Bit R2 Bit R2 Bit R2 Bit G2 Bit G2 Bit G2 Bit G2 Bit B2 Bit B2 Bit B2 Bit nd .co - m 8080-Series control 6800-Series control CSX - D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 1 0 0 w D12 - - .m R3 Bit R3 Bit R3 Bit R3 Bit G3 Bit G3 Bit G3 Bit G3 Bit B3 Bit B3 Bit B3 Bit R4 Bit R4 Bit R4 Bit R4 Bit G4 Bit G4 Bit G4 Bit G4 Bit B4 Bit B4 Bit B4 Bit R1 Bit w w R1 Bit R1 Bit R1 Bit G1 Bit G1 Bit G1 Bit G1 Bit B1 Bit B1 Bit B1 Bit Pixel n 12-bits B1 Bit Pixel n+1 12-bits B2 Bit Pixel n+2 B3 Bit Pixel n+3 B4 Bit Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits) 18-bits 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 12-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 146 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B (2). 18-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH="05h" There are 1 pixel (3 sub-pixels) per 1 bytes RESX IM1/IM0 CSX D/CX WRX RDX R/WX E D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 `1' IM1, IM0="11" `1' `0' 8080-Series control pins 6800-Series control pins - R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 nd .co R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 m R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 R3, Bi re R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B1, Bit 0 w w 0 0 1 0 1 1 0 0 w .m G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 16-bits bt Pixel n 16-bits Pixel n Pixel n Look-Up Table for 65K-colors or data mapping (16-Bits to 18-Bits) 18-bits 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 147 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B (3). 18-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH="06h" There are 1 pixel (6 sub-pixels) per 1 bytes RESX IM1/IM0 CSX D/CX WRX RDX R/WX E `1' IM1, IM0="11" `1' `0' 8080-Series control pins 6800-Series control pins D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 1 0 0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 nd .co R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit Pixel n+11 B2, Bit 0 m R3, Bit5 R4, Bit 5 R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 5 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit Pixel n+31 B4, Bit 0 R3, Bit5 re 148 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 5 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit Pixel n+21 B1, Bit 0 w Frame Memory w w .m G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, PixelBit 1 n B1, Bit 0 18-bits bt 18-bits R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 18-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.2. MCU Data Colour Coding for RAM data Read - Parallel 8-Bits Bus Interface (IM1, IM0= "00") Table 7.3.2.1 8-Bits Parallel Interface Set Table Register D17 D16 D15 D14 D13 D12 D11 D10 Command x x x x x x x x D17 D16 D15 D14 D13 D12 D11 D10 x x x x x x x x Read Data Format x x x x x x x x x x x x x x x x D9 x D9 x x x D8 x D8 x x x D7 0 D7 R5 G5 B5 D6 0 D6 R4 G4 B4 D5 1 D5 R3 G3 B3 D4 0 D4 R2 G2 B2 D3 1 D3 R1 G1 B1 D2 1 D2 R0 G0 B0 D1 1 D1 x x x D0 0 D0 x x x Command 2EH Colour 262K-Colour (1-pixels/ 3byyes) - Parallel 16-Bits Bus Interface (IM1, IM0= "01") Table 7.3.2.2 16-Bits Parallel Interface Set Table Register D17 D16 D15 D14 D13 D12 D11 D10 Command x x x x x x x x D17 D16 D15 D14 D13 D12 D11 D10 x x R5 R4 R3 R2 R1 R0 Read Data Format x x B5 B4 B3 B2 B1 B0 x x G5 G4 G3 G2 G1 G0 D9 x D9 x x x D8 x D8 x x x D7 0 D7 G5 R5 B5 D6 0 D6 G4 R4 B4 D5 1 D5 G3 R3 B3 m D4 0 D4 G2 R2 B2 D4 0 D4 R1 B4 D4 0 B4 nd .co D3 1 D3 G1 R1 B1 D2 1 D2 G0 R0 B0 D1 1 D1 x x x D0 0 D0 x x x Command 2EH Colour 262K-Colour (2-pixels/ 3byyes) - Parallel 9-Bits Parallel Interface (IM1, IM0= "10") - Parallel 18-Bits Parallel Interface (IM1, IM0= "11") Table 7.3.2.4 18-Bits Parallel Interface Set Table Register D17 D16 D15 D14 D13 D12 D11 D10 D9 Command x x x x x x x x x Read R5 R4 R3 R2 R1 R0 G5 G4 G3 Data Format Note . `x' Don't care, but need to set VDDI or DGND level. w w Table 7.3.2.3 9-Bits Parallel Interface Set Table Register D17 D16 D15 D14 D13 D12 D11 D10 Command x x x x x x x x D17 D16 D15 D14 D13 D12 D11 D10 Read x x x x x x x x Data Format x x x x x x x x .m bt D9 x D9 x x D8 x D8 R5 G2 D7 0 D7 R4 G1 D6 0 D6 R3 G0 D5 1 D5 R2 B5 D3 1 D3 R0 B3 re D2 1 D2 G5 B2 D1 1 D1 G4 B1 D0 0 D0 G3 B0 Register 2EH Colour 262K-Colour (1-pixels/ 2bytes) w D8 x G2 D7 0 G1 D6 0 G0 D5 1 B5 D3 1 B3 D2 1 B2 D1 1 B1 D0 0 B0 Register 2EH 262K-Colour (c) ORISE Technology Co., Ltd. Proprietary & Confidential 149 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.2.1. Parallel 8-Bits Bus Interface for RAM Data Read (IM1, IM0= "00") There are 1 pixels (3 sub-pixels) per 3-bytes. (RGB 6-6-6-bits output) RESX IM1/IM0 CSX D/CX RDX WRX R/WX E D7 D6 D5 D4 D3 D2 D1 D0 `1' IM1, IM0 = "00" `1' 8080-Series control pins m ----------------- `0' `1' 6800-Series control pins 0 0 1 0 1 1 1 0 nd .co R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 - G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 - B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 - w w w Dummy Pixel .m 150 bt re Frame Memory Pixel n 18-bits R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.2.2. Parallel 16-Bits Bus Interface for RAM Data Read (IM1, IM0= "01") There are 2 pixel (6 sub-pixels) per 3 bytes (RGB 6-6-6-bits output) RESX IM1/IM0 CSX D/CX RDX WRX R/WX E D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 `1' IM1, IM0 = "01" `1' 8080-Series control pins m --------------------------------- `0' `1' 6800-Series control pins 0 0 1 0 1 1 1 0 nd .co R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 - B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 - G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 - w w w Dummy Pixel Frame Memory .m bt 151 re Pixel n 18-bits Pixel n+1 18-bits R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.2.3. Parallel 9-Bits Bus Interface for RAM Data Read (IM1, IM0= "10") There are 1 pixel (3 sub-pixels) per 2 bytes (RGB 6-6-6-bits output) RESX IM1/IM0 CSX D/CX RDX WRX R/WX E D8 D7 D6 D5 D4 D3 D2 D1 D0 `1' IM1, IM0 = "10" `1' 8080-Series control pins m ------------------- `0' `1' 6800-Series control pins 0 0 1 0 1 1 1 0 nd .co R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 0 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 w w w Dummy Pixel .m bt re Pixel n Pixel n+1 18-bits 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 152 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.2.4. Parallel 18-Bits Bus Interface for RAM Data Read (IM1, IM0= "11") There are 1 pixel (3 sub-pixels) per 1 bytes (RGB 6-6-6-bits output) RESX IM1/IM0 CSX D/CX RDX WRX R/WX E D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 `1' IM1, IM0 = "11" `1' m ----------------------------------- 8080-Series control pins 6800-Series control pins `0' `1' 0 0 1 0 1 1 1 0 nd .co R1, Bit 5 R2, Bit 5 R3, Bit5 R3, Bit5 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 5 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B1, Bit 0 re bt R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 w .m w G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 w Dummy Pixel Frame Memory Pixel n 18-bits Pixel n+1 18-bits Pixel n+2 R1 G1 B1 R2 G2 B2 R3 G3 B3 Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 18-bits color depth information. Note 3. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential 153 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.3. Serial Interface (IM2 = `0') Different display data formats are available for three colors depth supported by the LCM listed below. - 4K-Colours, RGB 4,4,4-bits input data. (3AH="03h") - 65K-Colours, RGB 5,6,5-bits input data. (3AH="05h") - 262K-Colours, RGB 6,6,6-bits input data. (3AH="06h") 7.3.3.1. Write data for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH="03h" RESX IM2 CSX `1' Pixel n D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 1 D7 D6 D5 D4 nd .co D3 D2 D1 D0 D8 1 m Pixel n+1 D6 D5 D4 D3 D2 D1 D0 D7 B13 B12 B11 B10 R23 R22 R21 R20 G23 G22 G21 G20 B23 B22 B21 B20 `0' IM1,IM0= "xx" SDA SCL 1 R13 R12 R11 R10 G13 G12 G11 G10 12-bits Note 1. pixel data with the 12-bits color depth information Note 2. The most significant bits are: Rx3, Gx3 and Bx3 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 Note 4. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w 154 w Frame Memory .m 18-bits bt 18-bits Look-Up Table for 4K-colors mapping (12-Bits to 18-Bits) R1 G1 B1 R2 G2 B2 R3 G3 B3 re 12-bits Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.3.2. Write data for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH="05h" RESX IM2 CSX `1' `0' IM1,IM0= "xx" Pixel n D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 1 D7 D6 D5 D4 D3 D2 D1 D0 D8 1 D7 Pixel n+1 D6 D5 D4 D3 D2 D1 D0 G12 G11 G10 B14 B13 B12 B11 B10 R24 R23 R22 R21 R20 G25 G24 G23 SDA SCL 1 R14 R13 R12 R11 R10 G15 G14 G13 16-bits Look-Up Table for 65k-colors mapping (16-Bits to 18-Bits) 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1. pixel data with the 16-bits color depth information Note 2. The most significant bits are: Rx4, Gx5 and Bx4 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 Note 4. `-` = Don't care - Can be set to VDDI or DGND level 7.3.3.3. Write data for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH="06h" RESX IM2 CSX `1' `0' IM1,IM0= "xx" Pixel n D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 1 D7 D6 D5 D4 D3 D2 D1 D0 D8 1 D7 D6 D5 D4 D3 D2 D1 D0 - SDA SCL w w w .m bt G15 G14 G13 G12 G11 G10 B15 B14 B13 B12 B11 B10 1 R15 R14 R13 R12 R11 R10 18-bits Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1. pixel data with the 18-bits color depth information Note 2. The most significant bits are: Rx5, Gx5 and Bx5 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 Note 4. `-` = Don't care - Can be set to VDDI or DGND level (c) ORISE Technology Co., Ltd. Proprietary & Confidential re 155 nd .co Apr. 25, 2006 Preliminary Version: 0.1 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.3.3.4. Read data for Serial Interface (RGB 6-6-6-bits output) RESX IM2 Host `1' `0' IM1,IM0= "xx" CSX (SPI CSX) SCL SDA Driver 0 R2Eh High-Z SDA High-Z - D23 D22 D21 D20 D19 D18 D17 D16 D2 D1 D0 D23 D22 D21 D20 D19 9 Dummy Clock 1-Pixel data Read Data format as below R15 R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 - D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 nd .co D8 D7 D6 D5 D4 m D3 D2 D1 D0 B15 B14 B13 B12 B11 B10 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w 156 w w Note: `-` = Don't care - Can be set to VDDI or DGND level .m bt re Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4. 7.4.1. RGB interface General Description The module uses 6, 16 and 18-bits parallel RGB interface which includes: VS, HS, DE, PCLK, D[17:0]. The interface is activated after Power On sequence. Pixel clock (PCLK) is running all the time without stoping and it is used to entering VS, HS, DE and D[17:0] states when there is a rising edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g. Sleep In -mode etc. Vertical synchronization (VS) is used to tell when there is received a new frame of the display. This is negative (`0', low) active and its state is read to the display module by a rising edge of he PCLK signal. Horizontal synchronization (HS) is used to tell when there is received a new line of the frame. This is negative (`0', low) active and its state is read to the display module by a rising edge of the PCLK signal. Data Enable (DE) is used to tell when there is received a RGB information that should be transferred on the display. This is a positive (`1', high) active and its state is read to the display module by a rising edge of the PCLK signal. D[17:0] (18-bit: R5-R0, G5-G0 and B5-B0; 16-bit: R4-R0, G5-G0 and B4-B0) are used to tell what is the information of the image that is transferred on the display (When DE='1' and there is a rising edge of PCLK). D[17:0] can be `0' (low) or `1' (high). These lines are read by a rising edge of the PCLK signal. The PCLK cycle is described in the following figure. PCLK VS, HS, DE D[17:0] w Note: PCLK is an unsynchronized signal (It can be stopped). (c) ORISE Technology Co., Ltd. Proprietary & Confidential w Fig. 7.4.1 PCLK cycle w The host changes D[17:0], VS, HS and DE lines when there is a falling edge of the PCLK .m The driver read the D[17:0], VS, HS and DE lines when there is a falling edge of the PCLK bt 157 re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.2. General Timing Diagram Vertical Sync. 01 VS VBP Invisible Image = Timing information what is not possible to see on the display = Blanking Time DE = `0' (Low) Visible Image = Image which can see on the display = Active VP HDISP VFP Horizontal Sync. 1 0 HPW w .m HBP HP HDISP bt re nd .co HFP Apr. 25, 2006 Preliminary Version: 0.1 DE = `1' (high) The image information must be correct on the display, when the timings are in range on the interface. However, the image information can be incorrect on the display, when timings are not out of range on the interface (Out of the range timings cannot on the host side). The correct image information must be displayed automatically (by the display module) on the next frame (vertical sync.) when there is returned from out of the range to in range interface timing. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w Fig. 7.4.2 RGB General Timing diagram 158 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.3. Updating Order on Display Active Area (Normal Display Mode On + Sleep Out) There is defined different kind of updating orders for display. These updating orders are controlled by H/W (SMX, SMY) and S/W (MX, MY,) bits. Physical (0,0) Point Start Point (0,0) Vertical Active counter (0-219) Physical (0,0) Point Active areaa on the LCD Vertical Active counter (0-219) Active area on the LCD Start Point (0,0) End Point (175,219) Horizontal Active counter (0-175) Fig. 7.4.3.1 Updating order when MADCTL's MX='0' and MY = `0' bt re .m Physical (0,0) Point End Point (175,219) End Point (0,0) Vertical Active counter (0-219) Physical (0,0) Point Active area on the LCD Vertical Active counter (0-219) w w w Start Point (0,0) nd .co End Point (175,219) Fig. 7.4.3.2 Updating order when MADCTL's MX='1' and MY = `0' m Horizontal Active counter (0-175) Active area on the LCD Horizontal Active counter (0-175) Start Point (175,219) Horizontal Active counter (0-175) Fig. 7.4.3.4 Updating order when MADCTL's MX='1' and MY = `1' Fig. 7.4.3.3 Updating order when MADCTL's MX='0' and MY = `1' (c) ORISE Technology Co., Ltd. Proprietary & Confidential 159 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 7.4.3.1 Rules for Updating Order Condition An active VS signal is received Signal Pixel information of the active area is received An active HS signal between two active area lines The Horizontal counter is larger than 127 and the Vertical counter is larger than 159 Note 1. Pixel order is RGB on the display. Note 2. Data streaming direction from the host to the display is described in the following figure. Horizontal Counter Return to 0 Increment by 1 Return to 0 Return to 0 Vertical Counter Return to 0 No change Increment by 1 Return to 0 B Data Stream from RGB I/F is like in this figure ORISE Fig. 7.4.3.5 Data streaming order from RGB I/F (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 160 bt re nd .co Apr. 25, 2006 Preliminary Version: 0.1 E m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.4. RGB Interface Bus Width set All 4-kinds of bus width can be available during RGB interface mode (selected by COLMOD (3Ah) command for 8-bits, 16-bits and 18-bits data width) Table 7.4.4.1 RGB interface Bus Width Set Table VIPF[3:0] D17 D16 D15 D14 D13 D12 D11 D10 0101 0110 VIPF[3:0] 1110 R4 R5 R3 R4 R2 R3 R1 R2 R0 R1 x R0 G5 G5 G4 G4 D9 G3 G3 D9 x x x D8 G2 G2 D8 x x x D7 G1 G1 D7 R5 G5 B5 D6 G0 G0 D6 R4 G4 B4 D5 B4 B5 D5 R3 G3 B3 D4 B3 B4 D4 R2 G2 B2 D3 B2 B3 D3 R1 G1 B1 D2 B1 B2 D2 R0 G0 B0 D1 B0 B1 D1 x x x D0 x B0 D17 D16 D15 D14 D13 D12 D11 D10 x x x x x x x x x x x x x x x x x x x x x x x x D0 x x 6-bits data x Bus width 16-bits data 18-bits data Bus width Note 2: Only VIPF[3:0]= "0101","0110" and "1110" are valid on RGB I/F, Others are invalid. Note 3. `x' Don't care, but need to set VDDI or DGND level. 7.4.5. RGB Interface Mode Set RGB I/F Mode RGB Mode 1 RGB Mode 2 PCLK Used Used DE Used Used VS Used Used HS Used Used In RGB Mode 2 (RCM1, RCM0 = "11"), blanking porch setting of VS and HS signals are defined by RGBBPCTR (B5h) command. When DE pin is high, valid data is directly stored to frame memory. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w In RGB Mode 1 (RCM1, RCM0 = "10"), writing data to frame memory is done by PCLK and Video Data Bus (D[17:0]), when DE is high state. The external synchronization signals (PCLK, VS and HS) are used for internal display signals. So, controller (host) must always transfer PCLK, VS, HS and DE signals to SPFD54126B. w w There are 2-kinds of RGB mode which is selected by RCM1 & RCM0 hardware pins. .m bt Video Data bus D[17:0] Used Used re Table 7.4.5.1 RGB Interface Mode Set nd .co Register for Blanking Porch setting Not Used Used Reference clock for Display Internal Oscillator Internal Oscillator 161 Apr. 25, 2006 Preliminary Version: 0.1 m Note 1: When VIPF[3:0]="1110", 6-bits data width of 3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information. Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.6. RGB Interface Timing Diagram 7.4.6.1. General Timings for RGB I/F VIH VS VIL TVSST TVSST TVSHT HS VIH VIL THSST TPCLKCYC THSHT TPCLKHT TPCLKLT D[17:0] DE VIH VIL Fig. 7.4.6.1.1 General Timing for RGB I/F bt Table 7.4.6.1.1 General Timing for RGB I/F Item Pixel low pulse width Pixel high pulse width Vertical Sync. set-up time Vertical Sync. hold time Horizontal Sync. set-up time Horizontal Sync. hold time Data Enable set-up time Data Enable hold time Data set-up time Data hold time Symbol TPCLKLT TPCLKHT TVSST TVSSHT THSST TVSSHT TDEST TDEHT TDST TDHT re Condition Specification Type. nd .co TDST/TDEST TDHT/TDEHT m Min 15 15 15 15 15 15 15 15 15 15 Max Unit PCLK VIH VIL w .m Note 1: VDDI=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Note 3. Data lines can be set to "High" or "Low" during blanking time - Don't care. Note 4. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w ns ns ns ns w 162 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B VS HS PCLK DE * DE ** Data Bus Frame data N Frame N+1 Frame N+2 Frame Don't care Frame data Updating from Data bus Frame data Updating from SDA RAM write command (2Ch) (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m Fig. 7.4.6.1.2 RAM Access via SPI Interface in RGB Mode bt 163 DE* : RGB Mode 1 DE** : RGB Mode 2 Address set command (2Ah), (2Bh) Data transfer (ICM='1') re nd .co Data transfer (ICM='0') m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.6.2. RGB Interface Mode 1 Timing Diagram 1-Frame (TVP) V Back Porch (TVS+TVBP) VS HS DE V Front Porch (TVFP) 1-Line (THP) H Back Porch (THS+THBP) HS PCLK DE Data Bus Latch data RAM WEN In-Valid In-Valid Valid data area (THDISP) bt 164 re .m D1 D2 D3 D4 D5 Dn D1 D2 D3 D4 D5 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w Fig. 7.4.6.2.1 RGB Mode 1 Timing Diagram w nd .co Dn H Front Porch (THFP) m In-Valid Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Vertical Timing for RGB I/F VS TVFP TVS TVBP TVFP D [17:0] Note 3 TVBL TDSIP Note 3 DE TVP HS Horizontal Timing for RGB I/F HS THFP THS THBP THDSIP DE THBL TPCLK PCLK (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w Fig. 7.4.6.2.2 Vertical and Horizontal timing for RGB I/F .m bt THP 165 D [17:0] Note 3 re nd .co m THFP Note 3 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 7.4.6.2.1 Vertical and Horizontal Timing for RGB I/F Item Vertical Timing Symbol Condition Min Specification Type. Max Unit Vertical cycle period Vertical low pulse width Vertical front porch Vertical back porch Vertical data start line Vertical blanking period Vertical active area Vertical refresh rate Horizontal Timing Horizontal cycle period Horizontal low pulse width Horizontal front porch Horizontal back porch Horizontal data start point Horizontal blanking period Horizontal active area TVP TVS TVFP TVBP TVBL TVDISP TVRR THP THS THFP THBP GM="00" GM="01" GM="11" TVS + TVBP TVS + TVBP + TVFP GM="00" GM="01" GM="11" Frame rate 226 182 179 2 2 2 4 6 220 176 132 65 230 186 183 4 4 4 8 12 HS HS HS HS HS HS HS HS 61.75 208 2 2 2 30 1.0 32 68.25 512 256 256 256 256 256 Hz PCLK PCLK PCLK PCLK PCLK s PCLK PCLK ns MHz ns MHz ns MHz THS + THBP ffHS + fHBP THBL THDISP TPCLKCYC fPCLKCYC TPCLKCYC fPCLKCYC TPCLKCYC fPCLKCYC nd .co 100 2.82 100 2.27 100 1.72 m 176 Pixel clock cycle (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m GM="00" TVRR=65Hz GM="01" TVRR=65Hz GM="10" TVRR=65Hz 355 10 440 10 581 10 bt 166 re Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.6.3. RGB Interface Mode 2 Timing Diagram 1-Frame (TVP) V Back Porch (TVS+TVBP) VS HS DE V Front Porch (TVFP) H Back Porch (THS+THBP) HS PCLK DE Data Bus Latch data RAM WEN In-Valid In-Valid Valid data area (THDISP) re D1 D2 D3 D4 D5 bt 167 .m TVDISP= 220Hs D1 D2 D3 D4 D5 w w Fig. 7.4.6.3.1 RGB Mode 2 Timing Diagram TVS+TVBP = 3Hs VS w 1-Frame (TVP = 224Hs) HS Line 1 Line 220 DE Fig. 7.4.6.3.2 RGB Mode 2 Vertical Timing Diagram Note: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command. (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co H Front Porch (THFP) Dn In-Valid Dn TVFP = 1Hs m Apr. 25, 2006 Preliminary Version: 0.1 1-Line (THP) Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B -176xRGBx220 THP = 196 PCLK THS+THBP = 10PCLK HS THDISP = 176PCLK THFP = 10PCLK PCLK DE Data Bus In-Valid D1 D2 D3 D4 D5 Dn In-Valid Fig. 7.4.6.3.3 RGB Mode 2 Horizontal Timing Diagram IDM VS Data Bus Full-color mode .m bt Idle mode re 168 Note: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command. nd .co m Full-color mode Apr. 25, 2006 Preliminary Version: 0.1 Fig. 7.4.6.3.4 RGB Mode 2 Idle mode Timing Diagram (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Vertical Timing for RGB I/F VS TVFP TVS TVBP TVFP D [17:0] Note 3 TVBL TDSIP Note 3 DE TVP HS Horizontal Timing for RGB I/F HS THFP THS THBP THDSIP DE THBL Note 3 TPCLK THP re w .m bt 169 D [17:0] nd .co PCLK Fig. 7.4.6.3.5 Vertical and Horizontal timing for RGB I/F (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w m THFP Note 3 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 7.4.6.3.1 Vertical and Horizontal Timing for RGB I/F Item Vertical Timing Symbol Condition Min Specification Type. Max Unit GM="00" Vertical cycle period Vertical low pulse width Vertical front porch Vertical back porch Vertical data start line Vertical blanking period Vertical active area Vertical refresh rate Horizontal Timing Horizontal cycle period Horizontal low pulse width Horizontal front porch Horizontal back porch Horizontal data start point Horizontal blanking period Horizontal active area THBL THDISP TPCLKCYC fPCLKCYC TPCLKCYC fPCLKCYC TPCLKCYC fPCLKCYC TVP TVS TVFP TVBP TVBL TVDISP TVRR THP THS THFP THBP TVS + TVBP TVS + TVBP + TVFP GM="00" GM="01" GM="11" Frame rate GM="01" GM="11" 223 176 135 1 1 1 2 3 224 180 136 1 3 4 220 176 132 65 196 10 10 20 176 380 2.63 472 2.12 625 1.60 4 1023 1022 1023 1023 HS HS HS HS HS HS HS HS HS Hz PCLK PCLK PCLK PCLK PCLK s PCLK PCLK Ns MHz Ns MHz Ns MHz 61.75 176 1 1 1 2 TBD 3 100 2.40 100 1.92 100 1.45 m 68.25 511 63 63 62 63 256 418 10 520 10 690 10 Note 1. VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) (c) ORISE Technology Co., Ltd. Proprietary & Confidential w 170 w Note 2. Data lines can be set to "High" or "Low" during blanking time - Don't care. w .m Pixel clock cycle GM="00" TVRR=65Hz GM="01" TVRR=65Hz GM="10" TVRR=65Hz bt re THS + THBP ffHS + fHBP THS + THBP + THFP nd .co Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.6.4. Power On Sequence on RGB Mode 2 The Driver operates power up and display ON by VDD, VDDI, SHUT, VS, HS, DE, PCLK on RGB mode 2 as show as following figure. VDDI VDD RESX SHUT PCLK HS DE TVDD-VDDI TRS-SH TVDD-SH 1 2 3 nd .co 4 5 6 7 m 8 9 10 11 12 13 14 TPCLK -SH 15 Host Driver IC .m Display High Voltage Display Source Output VCOM Output Gate Output Internal Counter Internal oscillator bt re TSH-LCD VS Display ON TSH-ON w Display OFF Normal Display Normal Display w w Blanking Display (Over 1 frame display) Normal Display Fig. 7.4.6.4.1 Power On Sequence on RGB Mode 2 Table 7.4.6.4.1 Power ON AC Characteristics Characteristics Symbol Min Typ Max Unit Remark VDDI On to VDD On TVDDI-VDD 0 ns Note1 VDDI/VDD on to falling edge of SHUT TVDD-SH 1 ms RESX to falling of SHUT TRS-SH 10 us Signals input to falling edge of SHUT * TCLK-SH 1 PCLK Note2 Falling edge of SHUT to LCD power ON TSH-LCD 120 ms Falling edge of SHUT to Display start TSH-ON 10 VS Note 1: TVDDI-VDD can be <=0ns, >0ns. In any case, VDDI and VDD power up sequence should not have any impact on the driver / display functionalities / performance. Note 2: Signals mean VS, HS, DE and PCLK signal. Note 3: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command. (c) ORISE Technology Co., Ltd. Proprietary & Confidential 171 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.6.5. Power OFF Sequence on RGB Mode 2 The Driver operates power off and display OFF by VDD, VDDI, SHUT, VS, HS and DE on RGB mode 2 as show as following figure. VDDI VDD RESX SHUT PCLK HS DE VS TVDD-VDDI TOFF-VDD Host Driver IC Display High Voltage Display Source Output VCOM Output Gate Output Internal Counter Internal oscillator Display ON .m 0V 0V 172 bt Display OFF Normal Display w w Normal Display re w Normal Display Blanking Display (Over 1 frame display) Fig. 7.4.6.5.1 Power OFF Sequence on RGB Mode 2 Table 7.4.6.5.1 Power OFF AC Characteristics Characteristics Symbol Min Typ Max Unit Remark VDDI On to VDD On TVDDI-VDD 0 ns Note1 Signals input to VDDI/VDD off Toff-VDD 1 us Note2 Rising edge of SHUT to Display off TSH-OFF 2 VS Note 1: TVDDI-VDD can be <=0ns, >0ns. In any case, VDDI and VDD power up sequence should not have any impact on the driver / display functionalities / performance. Note 2: Signals mean VS, HS, DE and PCLK signal. Note 3: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command. (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co TSH-OFF m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.7. RGB Data Color Coding 7.4.7.1. 16-bits/pixel Colour Order on the RGB Interface RESX RCMx VS HS DE PCLK D17, R4 D16, R3 D15, R2 D14, R1 D13, R0 D12 D11, G5 D10, G4 D9, G3 D8, G2 D7, G1 D6, G0 D5, B4 D4, B3 D3, B2 D2, B1 D1, B0 D0 `1' RCM = `1' `1' `1' `1' R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 - R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 - R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 - R5, Bit 4 nd .co G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 - re 173 bt Pixel n+2 16-bits 18-bits .m w w B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 - w Pixel n 16-bits Pixel n+1 16-bits Pixel n+3 Look-Up Table for 65K-colors or data mapping (16-Bits to 18-Bits) Frame Memory 18-bits R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D23, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Green data and MSB=Bit4, LSB=Bit0 for Red and Blue data. Note 2. `-' Don't care, but need set to VDDI or DGND level. (c) ORISE Technology Co., Ltd. Proprietary & Confidential m R5, Bit 3 R5, Bit 2 R5, Bit 1 R5, Bit 0 - G5, Bit 5 G5, Bit 4 G5, Bit 3 G5, Bit 2 G5, Bit 1 G5, Bit 0 B5, Bit 4 B5, Bit 3 B5, Bit 2 B5, Bit 1 B5, Bit 0 - Pixel n+4 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.7.2. 18-bits/pixel Colour Order on the RGB Interface RESX RCM VS HS DE WRX D17, R6 D16, R5 D15, R4 D14, R3 D13, R2 D12, R1 D11, G5 D10, G4 D9, G3 D8, G2 D7, G1 D6, G0 D5, B5 D4, B4 D3, B3 D2, B2 D1, B1 D0, B0 `1' IM1='0' / IM0='0' `1' `1' `1' R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 R3, Bit 5 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 5 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 R4, Bit 5 R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 R5, Bit 5 re 174 bt Pixel n+2 18-bit .m w w w B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n Frame Memory 18-bit Pixel n+1 18-bit R1 G1 B1 R2 G2 B2 R3 G3 B3 Note 1: The data order is as follows, MSB=D23, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data. Note 2. `-' Don't care, but need set to VDDI or DGND level. (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 5 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3 m R5, Bit 4 R5, Bit 3 R5, Bit 2 R5, Bit 1 R5, Bit 0 G5, Bit 5 G5, Bit 4 G5, Bit 3 G5, Bit 2 G5, Bit 1 G5, Bit 0 B5, Bit 5 B5, Bit 4 B5, Bit 3 B5, Bit 2 B5, Bit 1 B5, Bit 0 Pixel n+4 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.4.7.3. 6-bits/pixel Colour Order on the RGB Interface RESX RCM VS HS DE WRX D17 D16 `1' IM1='0' / IM0='0' `1' `1' `1' - - - - - D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 - G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 - B1, Bit 5 nd .co R2, Bit 5 R2, Bit 4 R2, Bit 3 R1, Bit 2 R2, Bit 1 R2, Bit 0 - bt B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 - B1, Bit 4 re 175 .m w w w Pixel n 8-bit Frame Memory R1 G1 B1 R2 G2 B2 R3 G3 B3 Pixel n+1 Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data. Note 2. `-' Don't care, but need set to VDDI or DGND level. (c) ORISE Technology Co., Ltd. Proprietary & Confidential m - - G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 - Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5. 7.5.1. Display Data RAM Configuration The display module has an integrated 176x220x18-bit graphic type static RAM. This 696,960-bits memory allows to store on-chip a 176xRGBx220 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and interface Read or Write to the same location of the Frame Memory. Display Data RAM Organization (GM='00') LCD Glass (176 x RGB x 220) MPU I/F re 176 Look-up table Display Data RAM (176 x 220 x 18-bit) nd .co Latch Line Address Counter Scan Address Counter Apr. 25, 2006 Preliminary Version: 0.1 w Host Interface (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w Fig. 7.5.1.1 Display Date RAM Organization .m Column Address Counter Row Address Counter bt m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5.2. Memory to Display Address Mapping 7.5.2.1. When using 176RGB x 220 resolution (GM1, GM0 = "00", SMX=SMY=SRGB='0') Pixel 1 Pixel 2 -------- Pixel 175 Pixel 176 Gate Out Source Out S1 RGB=0 S2 RGB=1 S3 S4 RGB=0 S5 RGB=1 S6 -------RGB Order S523 S524 S525 S526 S527 S528 RGB=0 RGB=1 RGB=0 RGB=1 RA MY='0' MY='1' 1 2 3 4 5 6 7 8 | | | | | 213 214 215 216 217 218 219 220 0 1 2 3 4 5 6 7 | | | | | 212 213 214 215 216 217 218 219 CA 219 218 217 216 215 214 213 212 | | | | | 7 6 5 4 3 2 1 0 SA ML='0' ML='1' 0 1 2 3 4 5 6 7 219 218 217 216 215 214 213 212 | | | | | 7 6 5 4 3 2 1 0 R0 G0 B0 R1 G1 B1 --------------------------------------------------------| | | | | R174 G174 B174 R175 G175 B175 bt | | | | | | | | | | | | | | | | | | | | | | | | | re | | | | | nd .co | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | m 174 1 175 0 | | | | | 212 213 214 215 216 217 218 219 .m w w 0 175 1 174 ----------------------------------------------------------------------- MX='0' MX='1' Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command MX =Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command (c) ORISE Technology Co., Ltd. Proprietary & Confidential w 177 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5.2.2. When using 176RGB x 176 resolution (GM1, GM0 = "01", SMX=SMY=SRGB='0') Pixel 1 Pixel 2 -------- Pixel 175 Pixel 176 Gate Out Source Out S1 RGB=0 S2 RGB=1 S3 S4 RGB=0 S5 RGB=1 S6 -------RGB Order S523 S524 S525 S526 S527 S528 RGB=0 RGB=1 RGB=0 RGB=1 RA MY='0' MY='1' 1 2 3 4 5 6 7 | | | | | 170 171 172 173 174 175 176 0 1 2 3 4 5 6 | | | | | 169 170 171 172 173 174 175 CA 175 174 173 172 171 170 169 | | | | | 6 5 4 3 2 1 0 MX='0' MX='1' SA ML='0' ML='1' 0 1 2 3 4 5 6 175 174 173 172 171 170 169 | | | | | 6 5 4 3 2 1 0 R0 G0 B0 R1 G1 B1 ------------------------------------------| | | | | -------- R118 G118 B118 R119 G119 B119 nd .co | | | | | | | | | | | | | | | ---------------------------------------------------------------174 1 m | | | | | | | | | | | | | | | 175 0 re | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 169 170 171 172 173 174 175 w 0 175 w 1 174 Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command MX =Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command (c) ORISE Technology Co., Ltd. Proprietary & Confidential w .m 178 bt Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5.2.3. When using 176RGB x 132 resolution (GM1, GM0 = "11", SMX=SMY=SRGB='0') Pixel 1 Pixel 2 -------- Pixel 175 Pixel 176 Gate Out Source Out S7 RGB=0 S8 RGB=1 S9 S10 RGB=0 S11 S12 RGB=1 -------RGB Order S523 S524 S525 S526 S527 S528 RGB=0 RGB=1 RGB=0 RGB=1 RA MY='0' MY='1' 1 2 3 4 5 | | | | | 128 129 130 131 132 0 1 2 3 4 | | | | | 127 128 129 130 131 CA 131 130 129 128 127 | | | | | 4 3 2 1 0 MX='0' MX='1' SA ML='0' ML='1' 0 1 2 3 4 131 130 129 128 127 | | | | | 4 3 2 1 0 R0 G0 B0 R1 G1 B1 ----------------------------| | | | | -------- R174 G174 B174 R175 G175 B175 nd .co | | | | | | | | | | | | | | | -------------------------------------------------174 1 m | | | | | | | | | | | | | | | 175 0 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 127 128 129 130 131 0 175 Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command MX =Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command (c) ORISE Technology Co., Ltd. Proprietary & Confidential w 179 w w .m bt 1 174 re Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5.3. Normal Display On or Partial Mode On, Vertical Scroll Off 7.5.3.1. When using 176RGB x 220 resolution (GM1, GM0 = "00") In this mode, content of the frame memory within an area where column pointer is 00h to AFh and page pointer is 00h to DBh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). (1) Example for Normal Display On (MX=MY=ML='0' ,SMX=SMY='0') 176 Columns 00h 01h ---- ---- ---- ---- ---- AEh AFh 00h 01h 02h | | | | | | | | | | | | D9h DAh DBh Scan Order 0Z G1 0Z G2 2Z G3 3Z | 4Z | 4Z | 6Z | | | | | | | | | G218 G219 G220 00h 01h 02h | | | | | | | | | | | | D9h DAh DBh 176 Columns nd .co 176 RGB x 220 LCD Panel S0 U0 U1 V0 V1 W0 W1 X0 X1 Y0 Y1 Z0 Z1 V2 W2 X2 Y2 Y3 Z2 Z3 220 Lines 00 10 20 30 40 50 60 01 11 21 31 41 51 m 02 03 12 13 22 32 42 0W 0X 0Y 1W 0X 0Y 2X 2Y 3X 3Y 4X 4Y 5Y 00 10 20 30 40 50 60 01 11 21 31 41 51 02 03 12 13 22 32 42 0W 0X 0Y 1W 0X 0Y 2X 2Y 3X 3Y 4X 4Y 5Y 0Z G1 0Z G2 2Z G3 3Z | 4Z | 4Z | 6Z | | | | | | | | | G218 G219 G220 176 x 220 x18-bits Frame RAM S0 U0 U1 V0 V1 W0 W1 X0 X1 Y0 Y1 Z0 Z1 SZ UY UZ VX VY VZ WX WY WZ XX XY XZ YW YX YY YZ ZW ZX ZY ZZ Display area =220 lines 176 Columns w w (2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=D7h, MX=MV=ML='0' ,SMX=SMY='0') .m bt 00h 01h 02h | | | | | | | | | | | | D9h DAh DBh V2 W2 X2 Y2 Y3 Z2 Z3 SZ UY UZ VX VY VZ WX WY WZ XX XY XZ YW YX YY YZ ZW ZX ZY ZZ re 00 10 20 30 40 50 60 00h 01h ---- ---- ---- ---- ---- AEh AFh 00h 01h 02h | | | | | | | | | | | | D9h DAh DBh 220 Lines 00 10 20 30 40 50 60 01 11 21 31 41 51 02 03 12 13 22 32 42 0W 0X 0Y 1W 0X 0Y 2X 2Y 3X 3Y 4X 4Y 5Y w Scan Order 01 11 21 31 41 51 176 Columns 0Z G1 0Z G2 2Z G3 3Z | 4Z | 4Z | 6Z | | | | | | | | | G218 G219 G220 02 03 12 13 22 32 42 0W 0X 0Y 1W 0X 0Y 2X 2Y 3X 3Y 4X 4Y 5Y 0Z G1 0Z G2 2Z G3 3Z | 4Z | 4Z | 6Z | | | | | | | | | G218 G219 G220 Non-Display area =4 lines 176 x 220 x18-bits Frame RAM S0 U0 U1 V0 V1 W0 W1 X0 X1 Y0 Y1 Z0 Z1 SZ UY UZ VX VY VZ WX WY WZ XX XY XZ YW YX YY YZ ZW ZX ZY ZZ 176 RGB x 220 LCD Panel S0 U0 U1 V0 V1 W0 W1 X0 X1 Y0 Y1 Z0 Z1 SZ UY UZ VX VY VZ WX WY WZ XX XY XZ YW YX YY YZ ZW ZX ZY ZZ Display area =212 lines V2 W2 X2 Y2 Y3 Z2 Z3 V2 W2 X2 Y2 Y3 Z2 Z3 Non-Display area =4 lines (c) ORISE Technology Co., Ltd. Proprietary & Confidential 180 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5.3.2. When using 176RGB x 176 resolution (GM1, GM0 = "01") In this mode, contents of the frame memory within an area where column pointer is 00h to AFh and page pointer is 00h to AFh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). (1) Example for Normal Display On (MX=MY=ML='0', SMX=SMY='0') 176 Columns 00h 01h ---- ---- ---- ---- ---- AEh AFh 00h 01h 02h | | | | | | AEh AFh | | | | D9h DAh DBh Scan Order 00h 01h 02h | | | | | | AEh AFh 176 Columns 176 Columns w w (2) Example for Partial Display On (PSL[7:0]=03h,PEL[7:0]=ACh, MX=MV=ML='0', SMX=SMY='0') .m bt re No Used | | | | G218 G219 G220 00h 01h ---- ---- ---- ---- ---- AEh AFh 00h 01h 02h | | | | | | AEh AFh | | | | D9h DAh DBh 0W 0X 0Y 0Z G1 0X 0Y 0Z G2 2Y 2Z G3 3Y 3Z | 4Z | | 176 x 176 x18-bits Frame RAM | W0 WZ | X0 X1 XY XZ | Y0 Y1 Y2 YX YY YZ G175 Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G176 | | | | G218 G219 G220 176 Lines 00 10 20 30 40 01 02 03 11 12 21 31 w Scan Order 00h 01h 02h | | | | | | AEh AFh nd .co 176 Columns 00 10 20 30 40 01 02 03 11 12 21 31 0W 0X 0Y 0Z G1 0X 0Y 0Z G2 2Y 2Z G3 3Y 3Z | 4Z | | 176 x 176 x18-bits Frame RAM | W0 WZ | X0 X1 XY XZ | Y0 Y1 Y2 YX YY YZ G175 Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G176 176 Lines 00 10 20 30 40 01 02 03 11 12 21 31 0W 0X 0Y 0Z G1 0X 0Y 0Z G2 2Y 2Z G3 3Y 3Z | 4Z | | 176 RGB x 176 LCD Panel | W0 WZ | X0 X1 XY XZ | Y0 Y1 Y2 YX YY YZ G175 Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G176 00 10 20 30 40 01 02 03 11 12 21 31 0W 0X 0Y 0Z G1 0X 0Y 0Z G2 2Y 2Z G3 3Y 3Z | 4Z | | 176 RGB x 176 LCD Panel | W0 WZ | X0 X1 XY XZ | Y0 Y1 Y2 YX YY YZ G175 Z0 Z1 Z2 Z3 ZW ZX ZY ZZ G176 m Display area =176 lines Non-Display area =3 lines Display area =170 lines Non-Display area =3 lines No Used (c) ORISE Technology Co., Ltd. Proprietary & Confidential 181 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5.3.3. When using 176RGB x 132 resolution (GM1, GM0 = "11") In this mode, contents of the frame memory within an area where column pointer is 00h to AFh and page pointer is 000h to 83h is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). (1) Example for Normal Display On (MX=MY=ML='0' ,SMX=SMY='0') 176 Columns 00h 01h ---- ---- ---- ---- ---- AEh AFh 00h 01h 02h | | | | 82h 83h | | | | D9h DAh DBh Scan Order 0Y 0Z G1 0Y 0Z G2 2Y 2Z G3 3Z | | | XZ | YY YZ G131 ZY ZZ G132 | | | | G218 G219 G220 00h 01h 02h | | | | 82h 83h 176 Columns No Used 176 Columns w w (2) Example for Partial Display On (PSL[7:0]=02h,PEL[7:0]=81h, MX=MV=ML='0' ,SMX=SMY='0') .m bt re 00h 01h ---- ---- ---- ---- ---- AEh AFh 00h 01h 02h | | | 82h 83h | | | | D9h DAh DBh w Scan Order 00h 01h 02h | | | 82h 83h | | | | D9h DAh DBh nd .co 176 Columns 00 10 20 30 Y0 Y1 Y2 Z0 Z1 Z2 Z3 00 01 02 03 0W 0X 10 11 12 0X 20 21 30 176 x 132 x18-bits Frame RAM X0 Y0 Y1 Y2 YX Z0 Z1 Z2 Z3 ZW ZX 00 01 02 03 0W 0X 10 11 12 0X 20 21 30 176 RGB x 132 LCD Panel X0 Y0 Y1 Y2 YX Z0 Z1 Z2 Z3 ZW ZX 132 Lines 0Y 0Z G1 0Y 0Z G2 2Y 2Z G3 3Z | | | XZ | YY YZ G131 ZY ZZ G132 m Display area =132 lines 132 Lines 00 10 20 30 01 02 03 0W 0X 11 12 0X 21 31 176 x 132 x18-bits Frame RAM 0Y 0Y 2Y 3Y 0Z G1 0Z G2 2Z G3 3Z | Y0 Y1 Y2 Z0 Z1 Z2 Z3 | | YX YY YZ G131 ZW ZX ZY ZZ G132 | | | | G218 G219 G220 01 02 03 0W 0X 11 12 0X 21 31 176 RGB x 132 LCD Panel 0Y 0Y 2Y 3Y 0Z G1 0Z G2 2Z G3 3Z | Non-Display area =2 lines Display area =128 lines Non-Display area =2 lines | | YX YY YZ G131 ZW ZX ZY ZZ G132 | | | | G218 G219 G220 (c) ORISE Technology Co., Ltd. Proprietary & Confidential 182 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5.4. Vertical Scroll Mode There is vertical scrolling, which are determined by the commands "Vertical Scrolling Definition" (33h) and "Vertical Scrolling Start Address" (37h). T FA V SA T FA V SA B FA O riginal B FA Scrolling Fig. 7.5.4.1 Difference between Scrolling and original (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 183 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5.4.1. When using 176RGB x 220 resolution (GM1, GM0 = "00") When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=220. In this case, scrolling is applied as shown below. (1) Example for TFA =3, VSA=215, BFA=2, SSA=4, ML=0: Scrolling 176 Columns 00h 01h ---- ---- ---- ---- ---- AEh AFh 00h 01h 02h | | | | | | | | | | | | D9h DAh DBh Scan Order 0Z 1Z 2Z 3Z 4Z 5Z 6Z 1 2 3 | | | | | | | | | | | | 218 219 220 00h 01h 02h | | | | | | | | | | | | D9h DAh DBh 176 Columns 00h 01h ---- ---- ---- ---- ---- AEh AFh 220 Lines 00 10 20 30 40 50 60 01 11 21 31 41 51 02 03 12 13 22 32 42 0W 0X 0Y 1W 1X 1Y 2X 2Y 3X 3Y 4X 4Y 5Y SSA 00 10 20 40 50 60 01 11 21 41 51 02 03 12 13 22 42 0W 0X 0Y 1W 1X 1Y 2X 2Y 4X 4Y 5Y 0Z G1 1Z G2 2Z G3 4Z | 4Z | 6Z | | | | | | | | | | G218 G219 G220 TFA m 176 x 220 x18-bits Frame RAM T0 U0 U1 V0 V1 W0 W1 X0 X1 Y0 Y1 Z0 Z1 TZ UY UZ VX VY VZ WX WY WZ XX XY XZ YW YX YY YZ ZW ZX ZY ZZ 176 RGB x 220 LCD Panel T0 U0 U1 V0 V1 V2 W0 W1 W2 X0 X1 X2 30 31 32 Y0 Y1 Y2 Y3 Z0 Z1 Z2 Z3 TZ UY UZ VX VY VZ WX WY WZ XX XY XZ 3X 3Y 3Z YW YX YY YZ ZW ZX ZY ZZ VSA V2 W2 X2 Y2 Y3 Z2 Z3 nd .co bt re SSA 00h 01h 02h | | | | | | | | | | | | D9h DAh DBh BFA (2) Example for TFA =3, VSA=215, BFA=2, SSA=215, ML=1: Scrolling: TFA and BFT are exchanged 00h 01h 02h | | | | | | | | | | | | D9h DAh DBh 220 Lines 00 10 20 30 40 50 60 01 11 21 31 41 51 02 03 12 13 22 32 42 w 00h 01h ---- ---- ---- ---- ---- AEh AFh w 176 Columns w .m Scan Order 176 Columns 00h 01h ---- ---- ---- ---- ---- AEh AFh 0W 0X 1W 1X 2X 3X 4X 0Y 1Y 2Y 3Y 4Y 5Y 0Z 220 1Z 219 2Z 218 3Z | 4Z | 4Z | 6Z | | | | | | | | | 3 2 1 00 10 60 70 80 90 A0 01 02 03 11 12 13 61 62 71 81 0W 0X 0Y 1W 1X 1Y 6X 6Y 7Y 7Y 0Z G1 1Z G2 6Z G3 7Z | 8Z | 9Z | AZ | | | | | | | | | G218 G219 G220 BFA 176 x 220 x18-bits Frame RAM S0 U0 U1 V0 V1 W0 W1 X0 X1 Y0 Y1 Z0 Z1 SZ UY UZ VX VY VZ WX WY WZ XX XY XZ YW YX YY YZ ZW ZX ZY ZZ 176 RGB x 220 LCD Panel 20 30 40 50 X0 Y0 Z0 21 31 41 51 X1 Y1 Z1 22 32 42 X2 Y2 Y3 Z2 Z3 2X 2Y 2Z 3X 3Y 3Z 4X 4Y 4Z 5Y 4Z XX XY XZ YW YX YY YZ ZW ZX ZY ZZ VSA V2 W2 X2 Y2 Y3 Z2 Z3 TFA (c) ORISE Technology Co., Ltd. Proprietary & Confidential 184 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.5.5. Vertical Scroll Example Vertical Scroll Example (GM1, GM0 = "00") There are 2 types of vertical scrolling, which are determined by the commands " Vertical Scrolling Definition" (33h) and "Vertical Scrolling Start Address" (37h). Case 1: TFA + VSA + BFA220 N/A. Do not set TFA + VSA + BFA160. In that case, unexpected picture will be shown. Case 2: TFA + VSA + BFA=220 (Scrolling) Example1) When MADCTR parameter ML="0", TFA=0, VSA=220, BFA=0 and VSCSAD=80. VSCSAD 1 nd .co Increment Memory Physical Axis (0,0) Physical Line Pointer 2 re bt Physical Line Pointer 2 m Display Axis (0,0) 1 2 Frame Memory Display .m w Display Axis (0,0) 1 VSCSAD w 2 1 w Frame Memory Display Example2) When MADCTR parameter ML="1", TFA=30, VSA=190, BFA=0 and VSCSAD=80. Memory Physical Axis (0,0) Physical Line Pointer 2 Display Axis (0,0) 3 VSCSAD 3 2 TFA TFA 1 1 Frame Memory Increment Display Memory Physical Axis (0,0) Physical Line Pointer 2 Display Axis (0,0) VSCSAD 3 3 21 TFA TFA 1 Frame Memory Display (c) ORISE Technology Co., Ltd. Proprietary & Confidential 185 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.6. Address Counter The address counter sets the addresses of the display data RAM for writing and reading. (Example for GM1, GM0 = "00") Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 8-8-8-bit), according to the data formats. As soon as this pixel-data information is complete the "Write access" is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=175 (AFh) and Y=0 to Y=219 (DBh). Addresses outside these ranges are not allowed. Before writing to the RAM a window must be defined into which will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=175 (AFh), YE=219 (DBh). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For each image condition, the controls for the column and row counters apply as Fig. 7.6.1 below: Condition When RAMWR/RAMRD command is accepted Complete Pixel Read / Write action The Column counter value is larger than "End Column (XE)" Column Counter Return to "Start Column (XS)" Increment by 1 Return to "Start Column (XS)" Return to "Start Column (XS)" Row Counter Return to "Start Row (YS)" No change Increment by 1 Return to "Start Row (YS)" (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m The Column counter value is larger than "End Column (XE)" and the Row counter value is larger than "End Row (YE)" bt 186 re nd .co m For flexibility in handling a wide variety of display architectures, the commands "CASET, RASET" and "MADCTR" , define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Fig. 6.6.1 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.7. Memory Data Write/ Read Direction The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by "Memory Data Access Control" Command, bits B5 (MV), B6 (MX), B7 (MY) as described below. B Data Stream order is like in this figure ORISE E Fig. 7.7.1 Data streaming order MV MADCTR (36h) Virtual to Physical Pointer translator MX MY Virtual (0,0) when MV=don't care, MX='0', MY='0' Physical Column Pointer (0,0) .m RASET (2Bh) (0,219) bt Physical axes (175,219) Virtual (0,0) when MV=don't care, MX='1', MY='1' CASET (2Ah) MV 0 0 0 0 1 1 1 1 MX 0 0 1 1 0 0 1 1 MV 0 1 0 1 0 1 0 1 CASET Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (127-Physical Column Pointer) Direct to (127-Physical Column Pointer) Direct to Physical Row Pointer Direct to (159-Physical Row Pointer) Direct to Physical Row Pointer Direct to (159-Physical Row Pointer) w w Virtual (0,0) when MV=don't care, MX='0', MY='1' w Physical Row Pointer Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7 (MY), B6 (MX), B5 (MV). The write order for each pixel unit is D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 (c) ORISE Technology Co., Ltd. Proprietary & Confidential re 187 RASET Direct to Physical Row Pointer Direct to (219-Physical Row Pointer) Direct to Physical Row Pointer Direct to (219-Physical Row Pointer) Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (175-Physical Column Pointer) Direct to (175-Physical Column Pointer) nd .co (175,0) Virtual (0,0) when MV=don't care, MX='1', MY='0' m Apr. 25, 2006 Preliminary Version: 0.1 -When 176RGBx220 (GM='00') Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY) Display Data Direction Normal MADCTR Parameter MV MX MY 0 0 0 B Image in the Host (MPU) Image in the Driver (DDRAM) H/W position (0,0) B F Y-Mirror 0 0 1 B X-Y address (0,0) X: CASET Y: RASET E H/W position (0,0) F m B E E X-Mirror 0 1 0 nd .co E E B B F B E X-Y address (0,0) X: CASET Y: RASET H/W position (0,0) B E w F F F .m X-Mirror Y-Mirror 0 1 1 B bt re F X-Y Exchange 1 0 0 X-Y address (0,0) X: CASET Y: RASET H/W position (0,0) E H/W position (0,0) X-Y address (0,0) X: RASET Y: CASET E H/W position (0,0) X-Y address (0,0) X: RASET Y: CASET H/W position (0,0) B X-Y address (0,0) X: CASET Y: RASET w w B E E X-Y Exchange Y-Mirror 1 0 1 B E X-Y Exchange X-Mirror 1 1 0 B B F 1 1 1 B X-Y address (0,0) X: RASET Y: CASET E H/W position (0,0) E E X-Y address (0,0) X: RASET Y: CASET X-Y Exchange X-Mirror Y-Mirror F E B (c) ORISE Technology Co., Ltd. Proprietary & Confidential 188 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.8. Tearing Effect Output Line The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. 7.8.1. Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only: t vdl t vdh tvdl tvdh Vertical T im e Scale tvdh= The LCD display is not updated from the Frame Memory Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 162 H-sync pulses per field. t hd l thdl t h dh thdh bt re V -S ync th th V-S ync Invisible Line 1 st Line 2 nd Line .m nd .co 219 Line tvdl= The LCD display is updated from the Frame Memory (except Invisible Line - see below) thdh= The LCD display is not updated from the Frame Memory thdl= The LCD display is updated from the Frame Memory (except Invisible Line - see above) Bottom Line T op Line 2 nd Line T E (M ode2) T E (M ode1) t vdh w w w tvdh Note: During Sleep In Mode, the Tearing Output Pin is active Low. (c) ORISE Technology Co., Ltd. Proprietary & Confidential 189 m 220 Line Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.8.2. Tearing Effect Line Timings The Tearing Effect signal is described below: t vdl tvdl t vdh tvdh Vertical T im ing H orizontal T im ing t hd l thdl t hd h thdh Table 7.8.2.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 58.9 Hz) Symbol tvdl tvdh thdl thdh Parameter Vertical Timing Low Duration Vertical Timing High Duration min 13 nd .co 1000 33 25 m max 500 unit ms s s s description Horizontal Timing Low Duration Input Signal Slope TR w w Output Signal TF VIH=0.7*VDDI VIL=0.3*VDDI TR VOH=0.8*VDDI VOL=0.2*VDDI TF TR=TF<= 15ns w The signal's rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. .m NOTE: The timings in Table 7.8.2.1 apply when MADCTR ML=0 and ML=1 bt 190 Horizontal Timing High Duration Fig. 7.8.2.2 Rising and Falling timing for Input and Output signal The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect: (c) ORISE Technology Co., Ltd. Proprietary & Confidential re TR=TF<= 15ns Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.8.3. Example 1: MPU Write is faster than panel read. M CU to M em ory 1 st 162 nd tim e TE Output Signal tim e M em ory to LCD Im age on LCD 1 162 a b c d Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image: Data to be sent a w .m B w w b bt re c d 191 Im age on LCD AABB B (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co m st nd tim e Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.8.4. Example 2: MPU write is slower than panel read. M CU to M em ory 1 st 16 2 nd tim e TE Output Signal tim e M em ory to LCD Im age on LCD 1 st a b c d Data to be sent a w B w b .m bt c re The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer "catches" the MPU to Frame memory write position. nd .co e f 16 2 nd m d e 192 tim e f Im age on LCD AAAAAB B (c) ORISE Technology Co., Ltd. Proprietary & Confidential w Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.9. Preset Values ORISE has already set all preset values in SPFD54126B. Any of these preset values do not need customer's SW support. 7.10. Power ON/OFF Sequence VDDI and VDD can be applied in any order. VDDI and VDD can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX. Note 1: There will be no damage to the display module if the power sequences are not met. Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. If RESX line is not held stable by host during Power On Sequence, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated below: 7.10.1. Case 1 - RESX Line is held High or Unstable by Host at Power On If RESX line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDD and VDDI have been applied - otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset. w TrPW = +/- no limit w w .m tfPW = bt 193 re VDD1 VDDI VDD2 VDD Time when the latter signal rises up to 90% of its Typical Value. e.g. When VDD2 comes later, This time is defined at the cross point of 90% of 2.5V/2.75V, not 90% of 2.3V. 2.75V,not 90% of Time when the former signal falls down to 90% of its Typical Value. e.g. When VDD2 falls earlier, This time is defined at the cross point of 90% of 2.5V/2.75V, not 90% of 2.3V. 2.75V,not 90% of tfPW!CS = +/- no limit CSX trPW!CS = +/- no limit CSX CSX !CS RESX H or L trPW!RES = + no limit RESX 30% !RES (Power down in Sleep Out mode) tfPW!RES1 = min.120ms RESX1 trPW!RES = + no limit RES 30% RESX !RES (Power down in Sleep In mode) tfPW!RES1 RESX TfpwRESX1 is applied to !RES falling in the Sleep Out Mode. tfPW!RES2 TfpwRESX2 is applied to !RES falling in the Sleep In Mode. RESX Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level. (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co +/- no limit tfPW!RES2 = min.0ns RESX2 m During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has been released. Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.10.2. Case 2 - RESX Line is Held Low by Host at Power On If RESX line is held Low (and stable) by the host during Power On, then the RESX must be held low for minimum 10sec after both VDD and VDDI have been applied. TrPW = +/- no limit tfPW +/- no limit = VDD1 VDDI VDD2 VDD Time when the latter signal rises up to 90% of its Typical Value. e.g. When VDD2 comes later, This time is defined at the cross point of 90% of 2.5V/2.75V, not 90% of 2.3V. 2.75V,not 90% of Time when the former signal falls down to 90% of its Typical Value. e.g. When VDD2 falls earlier, This time is defined at the cross point 2.75V,not 90% 90% of 2.3V. of 90% of 2.5V/2.75V, notof CSX tfPW!CS = +/- no limit trPW!CS = +/- no limit CSX CSX !CS H or L RESX trPW!RES = min.10s !RES RESX (Power down in Sleep Out mode) RESX1 tfPW!RES1 = min.120ms RESX trPW!RES = min.10s re w w w .m bt 194 !RES RESX (Power down in Sleep In mode) tfPW!RES1 !RES TfpwRESX1 is applied to RESX falling in the Sleep Out Mode. TfpwRESX2 is applied to RESX falling in the Sleep In Mode. tfPW!RES2 !RES Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level. 7.10.3. Uncontrolled Power Off The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an uncontrolled power off the display will go blank and there will not be any visible effects within (TBD) second on the display (blank display) and remains blank until "Power On Sequence" powers it up. (c) ORISE Technology Co., Ltd. Proprietary & Confidential nd .co RESX2 tfPW!RES2 = min.0ns m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.11. Power Level Definition 7.11.1. Power Level 6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 262,144 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out. In this mode part of the display is used with maximum 262,144 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out. 5. Sleep In Mode In this mode, the DC: DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe. In this mode, both VDD and VDDI are removed. when both Power supplies are removed. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only bt 195 re 6. Power Off Mode nd .co In this mode, part of the display is used but with 8 colors. m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.11.2. Power Flow Chart Normal display mode on = NORON Partial mode on = PTLON Idle mode off = IDMOFF Idle mode on = IDMON Sleep out = SLPOUT Sleep in = SLPIN Power on sequence HW reset SW reset NORON PTLON Sleep out Normal display mode on Idle mode off SLPIN NORON IDMON IDMOFF SLPIN Sleep out Normal display mode on Idle mode on SLPOUT .m IDMON w w Sleep out Partial mode on Idle mode off w bt re SLPIN SLPOUT Sleep in Partial mode on Idle mode off IDMOFF PTLON NORON Sleep out Partial mode on Idle mode on nd .co IDMON IDMON Sleep in Normal display mode on Idle mode on m SLPOUT Sleep in Normal display mode on Idle mode off PTLON IDMOFF IDMOFF SLPIN SLPOUT Sleep in Partial mode on Idle mode on PTLON NORON Sleep out Sleep in Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode. Note 2: There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power mode. (c) ORISE Technology Co., Ltd. Proprietary & Confidential 196 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.12. Gamma Curves Gamma Curve 1.0 0.9 0.8 0.7 0.6 Y 0.5 0.4 0.3 0.2 Gamma = 1.0 Gamma = 2.5 Gamma = 2.2 Gamma = 1.8 Optical Gamma Curve according to the GC0 to GC3 bit 0.1 0.0 0.0 0.1 0.2 0.3 0.4 0.5 X 0.6 nd .co 0.7 0.8 m 0.9 1.0 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w 197 w w .m bt re Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.13. Reset 7.13.1. Reset Value 7.13.1.1. Reset Table (Default Value, GM=00, 176RGB x 220) Item Frame memory Sleep In/Out Display On/Off Display mode (normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) Gamma setting RGB for 256, 4k and 65k Color Mode Partial: Start Address (PSL) Partial: End Address (PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area (TFA) Scroll: Scroll Area (VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address (SSA) Tearing: On/Off Tearing Effect Mode *3) Memory Data Access Control (MY/MX/MV/ML/RGB) Interface Pixel Color Format RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 After Power On Random In Off Normal Off Off 0000h 00AFh 0000h 00DBh GC0 See Section 6.14 0000h 00DBh Off 0000h 00DBh 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 After Hardware Reset No Change In Off Normal Off Off 0000h 00AFh 0000h GC0 See Section 6.14 0000h 00DBh Off 0000h 00DBh 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h 80h 62h 00DBh After Software Reset No Change In Off Normal Off Off 0000h 00AFh (175d) (when MV=0) 00DBh (219d) (when MV=1) 0000h 00DBh (219d) (when MV=0) 00AFh (175d) (when MV=1) m bt GC0 No Change 0000h 00DBh Off 0000h 00DBh 0000h 0000h Off 0 (Mode1) No Change No Change 08h No Change No Change 00h 00h 00h 38h 80h 62h Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied. Notes:2. Powered-On Reset finishes within 10s after both VDD & VDDI are applied. Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h 80h 62h re 198 nd .co Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.13.1.2. Reset Table (GM=01, 176RGB x 176) Item Frame memory Sleep In/Out Display On/Off Display mode (normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) Gamma setting RGB for 256, 4k and 65k Color Mode Partial: Start Address (PSL) Partial: End Address (PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area (TFA) Scroll: Scroll Area (VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address (SSA) Tearing: On/Off Tearing Effect Mode *3) Memory Data Access Control (MY/MX/MV/ML/RGB) Interface Pixel Color Format RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 After Power On Random In Off Normal Off Off 0000h 00AFh 0000h 00DBh GC0 See Section 6.14 0000h 00AFh Off 0000h 00AFh 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h 80h 62h After Hardware Reset No Change In Off Normal Off Off 0000h 00AFh 0000h 00DBh GC0 See Section 6.14 0000h 00AFh Off 0000h 00AFh 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 After Software Reset No Change In Off Normal Off Off 0000h 00AFh (175d) (when MV=0) 00AFh (175d) (when MV=1) 0000h 00AFh (175d) (when MV=0) 00AFh (175d) (when MV=1) nd .co GC0 No Change 0000h 00AFh Off 0000h 00AFh 0000h 0000h Off 0 (Mode1) No Change No Change 08h No Change No Change 00h 00h 00h 38h 80h 62h re 199 Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied. Notes:2. Powered-On Reset finishes within 10s after both VDD & VDDI are applied. Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h 80h 62h w .m bt m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.13.1.3. Reset Table (GM=11, 176RGB x 132) Item Frame memory Sleep In/Out Display On/Off Display mode (normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) Gamma setting RGB for 256, 4k and 65k Color Mode Partial: Start Address (PSL) Partial: End Address (PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area (TFA) Scroll: Scroll Area (VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address (SSA) Tearing: On/Off Tearing Effect Mode *3) Memory Data Access Control (MY/MX/MV/ML/RGB) Interface Pixel Color Format RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR ID1 ID2 ID3 After Power On Random In Off Normal Off Off 0000h 00AFh 0000h 00DBh GC0 See Section 6.14 0000h 0083h Off 0000h 0083h 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h 80h 62h After Hardware Reset No Change In Off Normal Off Off 0000h 00AFh 0000h 00DBh GC0 See Section 6.14 0000h 0083h Off 0000h 0083h 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 After Software Reset No Change In Off Normal Off Off 0000h 00AFh (175d) (when MV=0) 0083h (131d) (when MV=1) 0000h 0083h (131d) (when MV=0) 00AFh (175d) (when MV=1) nd .co GC0 No Change 0000h 0083h Off 0000h 0083h 0000h 0000h Off 0 (Mode1) No Change No Change 08h No Change No Change 00h 00h 00h 38h 80h 62h re 200 Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied. Notes:2. Powered-On Reset finishes within 10s after both VDD & VDDI are applied. Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w 6 (18-Bit/Pixel) 08h 00h 6 (18-Bit/Pixel) 00h 00h 00h 38h 80h 62h w .m bt m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.13.2. Module Input/Output Pins 7.13.2.1. Output or Bi-directional (I/O) Pins Output or Bi-directional pins TE D7 to D0 (Output driver) After Power On Low High-Z (Inactive) After Hardware Reset Low High-Z (Inactive) After Software Reset Low High-Z (Inactive) Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset. 7.13.2.2. Input Pins Input pins RESX CSX D/CX WRX RDX D7 to D0 P/SX During Power On Process See 6.10 Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid After Power On Input valid Input valid Input valid Input valid Input valid Input valid Input valid After Hardware Reset Input valid Input valid Input valid After Software Reset Input valid During Power Off Process See 6.10 Input invalid Input invalid Input invalid Input invalid Input invalid Input invalid nd .co Input valid Input valid Input valid re 201 Input valid (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt m Input valid Input valid Input valid Input valid Input valid Input valid Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.13.3. Reset Timing Shorter than 5s tRESW !RES RESX tREST Internal Status Normal Operation Resetting Initial Condition (Default for H/W reset) Table 7.13.3.1 Reset input timing VSS=0V, VDDI=1.6V to 3.6V, VDD=2.6V to 3.5V,Ta = -30 to 70C) Symbol tRESW tREST Parameter *1) Reset low pulse width *2) Reset complete time Related Pins RESX MIN 10 TYP MAX - m Note - Unit s nd .co - 5 - 120 When reset applied during Sleep in mode When reset applied during Sleep out mode ms ms Note 1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below. bt w 10s RESX Pulse Shorter than 5s Longer than 10s Between 5s and 10s re 202 Action Reset Rejected Reset Note 2. During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out -mode. The display remains the blank state in Sleep In -mode) and then return to Default condition for H/W reset. Note 4. Spike Rejection also applies during a valid reset pulse as shown below: w Note 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX. w .m 10s Reset starts (It depends on voltage and temperature condition.) Reset is accepted Note 5. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120msec. (c) ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.14. Colour Depth Conversion Look Up Tables 7.14.1. 4096 and 65536 Colour to 262,144 Colour Colour Look Up Table Outputs Frame Memory Data (6-bit) R005R004 R003 R002 R001 R000 R015R014 R013 R012 R011 R010 R025R024 R023 R022 R021 R020 R035R034 R033 R032 R031 R030 R045R044 R043 R042 R041 R040 R055R054 R053 R052 R051 R050 R065R064 R063 R062 R061 R060 R075R074 R073 R072 R071 R070 R085R084 R083 R082 R081 R080 R095R094 R093 R092 R091 R090 R105R104 R103 R102 R101 R100 R115R114 R113 R112 R111 R110 R125R124 R123 R122 R121 R120 R135R134 R133 R132 R131 R130 R145R144 R143 R142 R141 R140 R155R154 R153 R152 R151 R150 R165R164 R163 R162 R161 R160 R175R174 R173 R172 R171 R170 R185R184 R183 R182 R181 R180 R195R194 R193 R192 R191 R190 R205R204 R203 R202 R201 R200 R215R214 R213 R212 R211 R210 R225R224 R223 R222 R221 R220 R235R234 R233 R232 R231 R230 R245R244 R243 R242 R241 R240 R255R254 R253 R252 R251 R250 R265R264 R263 R262 R261 R260 R275R274 R273 R272 R271 R270 R285R284 R283 R282 R281 R280 R295R294 R293 R292 R291 R290 R305R304 R303 R302 R301 R300 R315R314 R313 R312 R311 R310 Default value after H/W Reset 4k Colour 000000 000100 001000 001100 010001 010101 011001 011101 100010 100110 101010 101110 110011 110111 111011 111111 65k Colour 000000 000010 000100 000110 001000 001010 001100 001110 010000 010010 010100 010110 011000 011010 011100 011110 100001 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111 RGBSET Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Look Up Table Input Data 4k Colour 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 65k Colour 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 RED (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m Not Used bt 203 re nd .co m Not Used Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Look Up Table Outputs Frame Memory Data (6-bit) G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 G165 G164 G163 G162 G161 G160 G175 G174 G173 G172 G171 G170 G185 G184 G183 G182 G181 G180 G195 G194 G193 G192 G191 G190 G205 G204 G203 G202 G201 G200 G215 G214 G213 G212 G211 G210 G225 G224 G223 G222 G221 G220 G235 G234 G233 G232 G231 G230 G245 G244 G243 G242 G241 G240 G255 G254 G253 G252 G251 G250 G265 G264 G263 G262 G261 G260 G275 G 274 G273 G272 G271 G270 G285 G 284 G283 G282 G281 G280 G295 G 294 G293 G292 G291 G290 G305 G 304 G303 G302 G301 G300 G315 G 314 G313 G312 G311 G310 Default value after H/W Reset 4k Colour 000000 000100 001000 001100 010001 010101 011001 011101 100010 100110 101010 101110 110011 110111 111011 111111 65k Colour 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 RGBSET Parameter 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Look Up Table Input Data 4k Colour 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 65k Colour 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 Colour GREEN (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 204 Not Used re nd .co m Not Used Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Colour Look Up Table Outputs Frame Memory Data (6-bit) G325 G324 G323 G322 G321 G320 G335 G334 G333 G332 G331 G330 G345 G344 G343 G342 G341 G340 G355 G354 G353 G352 G351 G350 G365 G364 G363 G362 G361 G360 G375 G374 G373 G372 G371 G370 G385 G384 G383 G382 G381 G380 G395 G394 G393 G392 G391 G390 G405 G404 G403 G402 G401 G400 G415 G414 G413 G412 G411 G410 G425 G424 G423 G422 G421 G420 G435 G434 G433 G432 G431 G430 G445 G444 G443 G442 G441 G440 G455 G454 G453 G452 G451 G450 G465 G464 G463 G462 G461 G460 G475 G474 G473 G472 G471 G470 G485 G484 G483 G482 G481 G480 G495 G494 G493 G492 G491 G490 G505 G504 G503 G502 G501 G500 G515 G514 G513 G512 G511 G510 G525 G524 G523 G522 G521 G520 G535 G534 G533 G532 G531 G530 G545 G544 G543 G542 G541 G540 G555 G554 G553 G552 G551 G550 G565 G564 G563 G562 G561 G560 G575 G574 G573 G572 G571 G570 G585 G584 G583 G582 G581 G580 G595 G594 G593 G592 G591 G590 G605 G604 G603 G602 G601 G600 G615 G614 G613 G612 G611 G610 G625 G624 G623 G622 G621 G620 G635 G634 G633 G632 G631 G630 Default value after H/W Reset 4k Colour 65k Colour 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 RGBSET parameter 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Look Up Table Input Data 4k Colour 65k Colour 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Not Used nd .co GREEN (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 205 re m Not Used Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Colour Look Up Table Outputs Frame Memory Data (6-bit) B005B004 B003 B002 B001 B000 B015B014 B013 B012 B011 B010 B025B024 B023 B022 B021 B020 B035B034 B033 B032 B031 B030 B045B044 B043 B042 B041 B040 B055B054 B053 B052 B051 B050 B065B064 B063 B062 B061 B060 B075B074 B073 B072 B071 B070 B085B084 B083 B082 B081 B080 B095B094 B093 B092 B091 B090 B105B104 B103 B102 B101 B100 B115B114 B113 B112 B111 B110 B125B124 B123 B122 B121 B120 B135B134 B133 B132 B131 B130 B145B144 B143 B142 B141 B140 B155B154 B153 B152 B151 B150 B165B164 B163 B162 B161 B160 B175B174 B173 B172 B171 B170 B185B184 B183 B182 B181 B180 B195B194 B193 B192 B191 B190 B205B204 B203 B202 B201 B200 B215B214 B213 B212 B211 B210 B225B224 B223 B222 B221 B220 B235B234 B233 B232 B231 B230 B245B244 B243 B242 B241 B240 B255B254 B253 B252 B251 B250 B265B264 B263 B262 B261 B260 B275B274 B273 B272 B271 B270 B285B284 B283 B282 B281 B280 B295B294 B293 B292 B291 B290 B305B304 B303 B302 B301 B300 B315B314 B313 B312 B311 B310 Default value after H/W Reset 4k Colour 000000 000100 001000 001100 010001 010101 011001 011101 100010 100110 101010 101110 110011 110111 111011 111111 65k Colour 000000 000011 000101 000111 001001 001011 001101 001111 010001 010011 010101 010111 011001 011011 011101 011111 100001 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111 RGBSET parameter 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Look Up Table Input Data 4k Colour 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 65k Colour 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 BLUE (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 206 Not Used re nd .co m Not Used Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.15. Sleep Out-Command and Self-Diagnostic Functions of the Display Module 7.15.1. Register Loading Detection Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from OTP (one-time programming memory) to registers of the display controller is working properly. There are compared factory values of the OTP and register values of the display controller by the display controller. If those both values (OTP and register values) are same, there is inverted (=increased by 1) a bit in "Read Display Self-Diagnostic Result (0Fh)" (=RDDSDR) (The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= increased by 1). The flow chart for this internal function is following: Sleep Out Mode Sleep In Mode nd .co m RDDSDR's D7=0 Sleep In (10h) Power on sequence HW reset SW reset No w (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w Are OTP and register values same ? Yes D7 inverted Note: There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh), by the display module. .m Loads values from OTP to registers Compares OTP and register values bt 207 re Sleep Out (11h) Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.15.2. Functionality Detection Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (only Booster voltage level). If functionality requirement is met, there is inverted (= increased by 1) a bit in "Read Display Self- Diagnostic Result (0Fh)" (= RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= increased by 1). The flow chart for this internal function is following: Sleep In (10h) Power on sequence HW reset SW reset Sleep Out (11h) No w w w Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In -mode to Sleep Out -mode, before there is possible to check if functionality requirements are met and a value of RDDSDR's D6 is valid. Otherwise, there is 5msec delay for D6's value, when Sleep Out -command is sent in Sleep Out -mode. (c) ORISE Technology Co., Ltd. Proprietary & Confidential .m Is functionality requirement met ? D6 inverted bt Checks Booster voltage levels and other functionalities Yes re 208 nd .co Sleep Out Mode Sleep In Mode m RDDSDR's D6=0 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.15.3. Chip Attachment Detection Sleep Out-command is a trigger for an internal function of the display module, which indicates, if a chip or chips (e.g. driver, etc.) of the display module is/are attached to the circuit route of a flex foil or display glass ITO. There is inverted (= increased by 1) a bit in command "Read Display Self- Diagnostic Result (0Fh)" (= RDDSDR) (The used bit of this command is D5), if the chip or chips is/are attached to the circuit route of the flex or display glass. If this chip is or those chips are not attached to the circuit route of the flex or display glass, this bit (D5) is not inverted (= increased by 1). The following figure is for reference purposes; how this chip attachment can be implemented e.g. there are connected together 2 bumps via route of ITO or the flex foil on 4 corners of the driver (chip). Bump Substrate of display glass bt The flow chart for this internal function is following: re nd .co Routing between bumps m Through view of driver to Routing between bumps w Sleep Out Mode w .m Sleep In (10h) Power on sequence HW reset SW reset Sleep In Mode RDDSDR's D5=0 w Sleep Out (11h) Checks, if chip is attached to route No Is chip attached to routes? Yes D5 inverted (c) ORISE Technology Co., Ltd. Proprietary & Confidential 209 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.15.4. Display Glass Break Detection Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display glass of the display module is broken or not. There is inverted (= increased by 1) a bit in "Read Display Self-Diagnostic Result (0Fh)" (= RDDSDR) (The used bit of this command is D4), if the display glass is not broken. If this display glass is broken, this bit (D4) is not inverted (= increased by 1). The following figure is a reference, how this glass break detection can be implemented e.g. there is connected together 2 bumps via route of ITO. This route of ITO is the nearest route of the edge of the display glass. Active area of the display glass Through view of driver to Substrate of display glass The flow chart for this internal function is following: w .m bt re nd .co Power on sequence HW reset SW reset RDDSDR's D4=0 Apr. 25, 2006 Preliminary Version: 0.1 w w Sleep In (10h) Sleep Out Mode Sleep In Mode Sleep Out (11h) Checks, if display glass is broken Yes Is the display glass broken? No D4 inverted (c) ORISE Technology Co., Ltd. Proprietary & Confidential 210 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.16. Oscillator The chip has on-chip oscillator that does not require external components. This oscillator output signal is used for system clock generation for internal display operation. 7.17. System Colck Generator The timing generator produces the various signals to dirver the internal circuitty. Internal chip operation is not affected by operations on the data bus. 7.18. Instruction Decoder and Register The instruction decoder indentifies command words arriving at the interface and routes the following data bytes to their destination. The command set can be found in " Command" section. The source driver block includes 176x3 source outputs (S1 to S528), which should be connected directly to the TFT-LCD. The source output signals are generated in the data processing block after the data is read out of the RAM and latched, which represent the simulatance selected rows. 7.20.1. Gate Driver S1-S528 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 1 2 3 4 .m 5 bt 6 The gate dirver block include 220 chanel gate output (G1 to G220) which should be connected directly to the TFT-LCD. re 7 7.20. Gate Driver nd .co 8 9 VGH 7.19. Source Driver m 10 11 12 w w w VGL Fig. 7.20.1 Gate Driver Output Option 1 (c) ORISE Technology Co., Ltd. Proprietary & Confidential 211 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.21. -CORRECTION FUNCTION The SPFD54126B adopts true 6-bit OP-AMP with adjustable -correction function to display in 262,144 colors. The adjustable -correction can be set by 10 groups of registers to determine eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment registers. Each register group can be set independently to other register groups. 7.22. VSYNC Interface The SPFD54126 incorporates a VSYNC-I/F, which enables to display a moving picture with only a system interface and frame-synchronizing signal (VS). This interface enables to display moving pictures with minimum modification to a conventional system. Host RESX TE VS SPFD54126 RESX TE VS `0' `0' `0' CSX D/CX (SCL) WRX (R/WX) RDX (E) D7 to D1 D0 "0" "0" SCL SDA SPI_CSX bt `0' or `1' "00" DGND .m w IM2 = `1' Note: RCM = `01' IM2='1', MCU I/F P68='0', 8080-MCU I/F P68='1', 6800-MCU I/F w Fig. 7.21.1 VSYNC Interface for 8-bits data bus (Example) The VSYNC-I/F is truned ON by VSYNC-I/F ON (ADH) command and turned OFF by VSYNC-I/F OFF (ACH) command. In VSYNC-I/F mode, internal display operations are synchronized with VS. The VSYNC-I/F enables to display a moving picture through a system interface and update screens without flicker by writing data to RAM through a system interface in higher speed than the internal display operations by some degree. The VSYNC-I/F executes display operations only with internal clocks generated by internal oscillators and VS input. All display data are stored in RAM so that only the data relevant to updating a screen are transferred to minimize data transmission while displaying a moving picture. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w re 212 nd .co CSX D/CX WRX (R/WX) D7 to D1 RDX (E) D0 D15 to D8 D17 to D16 P68 IM1, IM0 IM2 HS, DE RPCLK m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B - Leading Mode (1) (2) (3) (4) (5) (6) (7) Internal Frame Sync. Signal L1 1 Frame L220 L1 L90 L1 L220 L1 L220 L1 L90 L1 L220 Display Operation External VS Signal RAM Update Write D[B:0] A 14H 2H 14H A 14H B 2H 14H B 2H 14H B 14H C 2H > 1H L1 > 1H L1 B > 2H < 1Frame C > 2H nd .co (3) (4) A BB B B CC (1) (2) (1) (6) m (7) - Lagging Mode (1) (2) 1 Frame L1 L90 L1 bt re (3) (4) (5) (6) .m Internal Frame Sync. Signal Display Operation External VS Signal RAM Update Write D[B:0] L220 L1 L220 L1 L90 L1 L220 L1 L220 w A 14H 14H > 16H A B 2H 14H B 14H > 16H B 2H 14H C 2H 2H 14H w > 1H w > 1H L1 L1 B > 2H > 1Frame C > 2H > 1Frame A (1) A (2) B (3) B (4) B (5) C (6) 1. In RCM1, RCM0 = "01" mode, writing data to RAM on rising edge of VS signal 2. If high pulse of VS signal shoule large than 1-lines. 3. The BP and FP should follow conditions : BP 2-lines , FP2-lines and BP+FP = 16-lines 4. The signals (CSX, WRX, D/CX and VS) of VSYNC I/F should follow MCU Parallel Interface AC timing. 5. B=17. (c) ORISE Technology Co., Ltd. Proprietary & Confidential 213 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B The VSYNC-I/F has limits on the minimum RAM write speed through the system interface and the frequency of the internal clocks. It requires a RAM write speed more than the calculated result from the following formula. - Internal clock frequency (fosc) [Hz] = Frame Frequency x (DisplayLines +Front Porch(VSFP)+BackPorch (VSBP)) x 16(clocks) x fluctuation RAM Write Speed (Min) (Hz) = 176 x Display Line (220 Line) BackPorch (VSBP ) + Display Line - m arg ins ) x16 (clocks ) x 1 fosc Example of RAMs writes speed and the frequency of the internal clocks in VSYNC-I/F mode is as follows. Example: Display size: 176 RGB x 220 lines Raster-rows: 220 lines Back/ Front porch: 14/ 2 lines (VSBP = 1110/ VSFP = 0010 of AFH) -When Frame frequency: 60 Hz Internal clock frequency (fosc) [Hz] = 60Hz x (220+2+14) lines x 16 Clocks x 1.1 / 0.9 = 277kHz Also in this example, variations attributed to LSI fabrication and room temperature are taken into consideration as causes of fluctuations. Other possible causes of fluctuations, such as variations in external resistors or voltage changes are not considered in this example. It is necessary to make a setting with enough margins to accommodate -When Frame frequency: 60Hz Minimum speed for RAM writing [Hz] > 176 x 220 / {((14+220-2) lines x 16 clock) / 300 kHz} = 2.89MHz Note 2: The above calculation is premised on the case of writing data to RAM on the falling edge of VS. Note 3: There must at least be a margin of 2 processing lines when all one-frame data are written to RAM before the SPFD54126 starts processing display lines. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w When calculating an internal clock frequency, possible causes of fluctuations must also be taken into consideration. In this example, the allowance for the fluctuation is 10 % from the center value, and the frequency must be within a VS cycle. w w .m 214 bt re nd .co m Note 1: When RAM write does not start right after the falling edge of VS, the time from the falling edge of VS until RAM write starts must also be taken into account. Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B By writing data to RAM on rising edge of VS signal at speed of 2.89MHz (Frame rate=60Hz) or more, it is possible to overwrite an entire screen without flicker by completing data write operation of a line before it starts display operation of that line. RAM write at 10MHz 38,720 times RAM write at 2.89MHz Line Processing VS Back Porch (14-lines) RAM Write Display Operation Display (220-lines) Lines 220 RC oscillation 10% Display Operation Display Operation m 13.41 Display Operation 11.17 13.55 Front Porch (2-lines) Blanking period 0 Back porch (14-lines) VS 4.22 ms 13.55 16.74 (60Hz) Fig. 7.28.3 Write/Display Operation Timing via VSYNC-I/F Notes to the VSYNC Interface w w 2. The aforementioned example of calculation is the value in case of overwriting full screen. If a moving picture display area is limited, it will result in more margins between RAMs write and display operations. RC oscillation 10% Display Operation RAM write at 3.15MHz VS w Back Porch (14-lines) 16-lines RAM Write Display Operation Moving picture area (188-lines) 16-lines Front Porch (2-lines) Blanking period 17 0 Back porch (14-lines) VS Line Processing .m 1. The aforementioned example of calculation is just a result of calculation. In actual settings, possible causes of fluctuations should be taken into consideration. It is necessary to give enough margins when setting a RAM writing speed. bt Lines 220 205 re nd .co ms 16.74 (60Hz) Fig. 7.28.4 RAM write speed margin 3. A front porch period continues after completion of 1 frame and until the next input of VS. 4. The partial display and vertical scroll functions are not available with the VSYNC-I/F. (c) ORISE Technology Co., Ltd. Proprietary & Confidential 215 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 8. ELECTRICAL SPECIFICATIONS 8.1. DC CharacteristicAC Characteristic (VDD=2.6V~3.0V, VDDIO = 1.6V~3.0V, Ta = -40 ~ 85) Parameter Power & Operation Voltage Analog Operating voltage Logic Operating voltage Gate Driver High voltage Gate Driver Low voltage Driver Supply voltage Input / Output Logic High level input voltage Logic Low level input voltage Logic High level output voltage Logic Low level output voltage Logic High level input current Logic Low level input current Logic Input leakage current VCOM Operation VCOM High voltage VCOM Low voltage VCOM Amplitude voltage Source Driver Source output range Gamma reference voltage Symbol VDD VDDI VGH VGL Conditions Operating Voltage I/O supply voltage- MIN 2.6 1.6 10.0 -11.5 19 Specification TYP MAX 2.78 1.8/2.78 3.5 3.6 13.5 -9.0 30 VDDI 0.3VDDI VDDI 0.2VDDI 1 +0.1 5.0 0.0 6.0 AVDD-0.1 Unit Related Pins V V V V V V V V V A A A V V V V V s |VGH-VGL| VIH VIL VOH VOL IIH IIL IIL VCOMH VCOML VCOMA VSout GVDD Tr Note 2 Note 2 Note 3 Note 3 Note 3 Note 1, 2, 3 Note 1, 2, 3 Note 1, 2, 3 Note 1, 2, 3 Note 1, 2, 3 Note 1, 2, 3 Note 1, 2, 3 Note 3 Note 3 Note 3 Note 4 Note 3 Note 4, 5 Note 4 Note 6 Note 3 Note 3 Note 3 IOH = -1.0mA IOL = +1.0mA VIN = VDDI or VSS Ccom=19nF Ccom=19nF |VCOMH-VCOML| re .m bt nd .co VSS -1 -0.1 2.5 -2.5 4.0 0.1 3.0 25 4.75 *6) 0.2 0.8VDDI m - 0.7VDDI VSS - w Source output settling time Output deviation voltage (Source output channel) Output offset voltage Booster Operation Internal reference voltage 1st Booster (VDDx2) voltage 1st Booster (VDDx2) Drop voltage Linear range w 5.0 30 20 15 35 1 5.5 *7) 5% AVDD-0.2 Below with 99% precision Sout >=4.2V, Sout<=0.8V 4.2V>Sout>0.8V w V,dev VOFSET mV mV mv % V % V VREF AVDD VDDx2,d rop I AVDD = 1.3mA (include Panel loading) VLinear Note 1: VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) Note 2, 3, 4: When the measurements are performed with LCD module, Measurement Points are like below. Note 3: CSX, RDX, WRX, D[17:0], D/CX, RESX, TE, PCLK, P/SX, VS, HS, DE, DIN, DOUT, SCL, GM1, GM0, LCM, RCM, P68, IM2, IM1, IM0, SRGB, SINV, SMX, SMY and Test pins Note 5, Source channel loading= 15pF/channel, Gate channel loading= 50pF/channel. Note 6, The Max. value is between with Note 4 measure point and Gamma setting value. (c) ORISE Technology Co., Ltd. Proprietary & Confidential 216 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 8.2. 8.2.1. AC timing Characteristics Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (8080-series MCU) TCHW TCHW VIH VIL CSX TCSF TCS TCSH TCSF D/CX VIH VIL TAST TWC TAHT TWRH D[17:0] Write TAST VIH VIH VIL TRCS/TRCSFM TRDL/TRDLFM re MIN 10 10 0 35 45 355 10 10 100 35 35 160 90 45 450 90 355 10 10 40 340 80 MAX Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TRC/TRCFM bt .m VIH VIL RDX D[17:0] Read VIL nd .co 20 TDST TRAT/ TRATFM Fig. 8.2.1.1 Parallel Interface characteristics (8080-Series MCU) Signal D/CX Symbol TAST TAHT TCHW TCS TRCS TRCSFM TCSF TCSH TWC TWRH TWRL TRC TRDH TRDL TRCFM TRDHFM TRDLFM TDST TDHT TRAT TRATFM TODH w Table 8.2.1.1: AC Characteristics for Parallel Interface18, 16, 9, 8-bits bus (8080-series MCU) Parameter Description Address setup time Address hold time (Write/Read) Chip select "H" pulse width Chip select setup time (Write) Chip select setup time (Read ID) Chip select setup time (Read FM) Chip select wait time (Write/Read) Chip select hold time Write cycle Control pulse "H" duration Control pulse "L" duration Read cycle (ID) Control pulse "H" duration (ID) Control pulse "L" duration (ID) Read cycle (FM) Control pulse "H" duration (FM) Control pulse "L" duration (FM) Data setup time Data hold time Read access time (ID) Read access time (FM) Output disable time w w CSX WRX RDX (ID) RDX (FM) D[17:0] Note 1: VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) (c) ORISE Technology Co., Ltd. Proprietary & Confidential 217 Apr. 25, 2006 Preliminary Version: 0.1 m TAHT WRX VIH VIL TWRL TDHT TRDH/ TRDHFM TODH -(3-transfer for one pixel) When read ID data When read from frame memory For maximum CL=30pF For minimum CL=8pF Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Input Signal Slope TR VIH=0.7*VDDI VIL=0.3*VDDI TF Output Signal TR VOH=0.8*VDDI VOL=0.2*VDDI TF TR=TF<= 15ns TR=TF<= 15ns Fig. 8.2.1.2 Rising and Falling timing for Input and Output signal CSX VIH VIL nd .co VIH VIL TCSF Fig.8.2.1.3 Chip selection (CSX) timing WRX VIH VIL w CSX w w .m bt 218 WRX RDX re Min. 5ns VIH VIL RDX TWRH VIH VIL TWRH /TRDHFM Fig. 8.2.1.4 Write to read and Read to write timing NOTE: The input signal rise time and fall time (Tr, Tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. (c) ORISE Technology Co., Ltd. Proprietary & Confidential m TCHW Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 8.3. Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (6800-series MCU) TCHW CSX VIH VIL TCS TRCS/TRCSFM TCSH TCSF VIH D/CX /WX E D[17:0] Write RX E D[17:0] Read VIL TAST VIH VIL VIH VIL VIH VIL TAHT TWC TWRL VIH VIL VIH VIL TRC/TRCFM TRDH/ TRDHFM VIH VIL Fig. 8.3.1 Parallel Interface characteristics (6800-Series MCU) Table 8.3.1: AC Characteristics for Parallel Interface 18, 16, 9, 8-bits bus (6800-series MCU) Signal D/CX Symbol TAST TAHT TCHW TCS TRCS TRCSFM TCSF TCSH TWC TWRH TWRL TRC TRDH TRDL TRCFM TRDHFM TRDLFM TDST TDHT TRAT TRATFM TODH w w Parameter .m bt TRAT/ TRATFM re TODH MIN 10 10 0 35 45 355 10 10 100 35 35 160 90 45 450 90 355 10 10 40 340 80 MAX Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns - TRDL/TRDLFM nd .co Description When read ID data When read from frame memory For maximum CL=30pF For minimum CL=8pF 20 Apr. 25, 2006 Preliminary Version: 0.1 TDST TDHT CSX WRX RDX (ID) RDX (FM) D[17:0] Address setup time Address hold time (Write/Read) Chip select "H" pulse width Chip select setup time (Write) Chip select setup time (Read ID) Chip select setup time (Read FM) Chip select wait time (Write/Read) Chip select hold time Write cycle Control pulse "H" duration Control pulse "L" duration Read cycle (ID) Control pulse "H" duration (ID) Control pulse "L" duration (ID) Read cycle (FM) Control pulse "H" duration (FM) Control pulse "L" duration (FM) Data setup time Data hold time Read access time (ID) Read access time (FM) Output disable time Note 1: VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w 219 m TWRH Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 8.4. Serial Interface Characteristics (3-pin Serial) CSX VIH VIL TCHW TCSS TSCYCW /TSCYCR TSLW /TSLR TSHW /TSHR TSDH TCSH TSCC SCL VIH VIL TSDS SDA (DIN) SDA (DOUT) VIH VIL VIH VIL TACC TOH Fig. 8.4.1 3-pin Serial Interface Characteristics w .m CSX SCL SDA (DIN) (DOUT) TCSS TCSH TSCC TCHW TSCYCW TSHW TSLW TSCYCR TSHR TSLR TSDS TSDH TACC TOH Chip select setup time Chip select hold time Chip select setup time Chip select setup time Serial clock cycle (Write) SCL "H" pulse width (Write) SCL "L" pulse width (Write) Serial clock cycle (Read) SCL "H" pulse width (Read) SCL "L" pulse width (Read) Data setup time Data hold time Access time Output disable time bt Signal Symbol Parameter re Table 8.4.1: 3-pin Serial Interface Characteristics nd .co MIN 60 65 20 40 100 35 35 150 60 60 30 30 10 15 MAX Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description For maximum CL=30pF For minimum CL=8pF Apr. 25, 2006 Preliminary Version: 0.1 Note 1: VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w 220 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 9. PAD LOCATIONS 9.1. PAD Assignment Chip Information: Basic Information: Chip Size: 18650 um x 950 um Chip thickness: 300um(Typ) Coordinates origin: Pad Left-bottom side Au Bump: Height = 15um (Typ) 1. Output Pads Boundary (Include Scribe Land) PADA1 PADB1 PADA0 VOTP VOTP EXTC V D D IO IM 0 IM 1 IM 2 P68 DGNDO S P I_ C S X DUMMY DUMMY V D D IO RCM0 RCM1 DGNDO SRGB SMX SMY V D D IO PREG RL TB SHUT ID M REV DGNDO GM1 GM0 V D D IO DUM DUM G G M M Y Y 219 215 PADB4 PADA4 DUMMY G 217 G 213 F E D A C B Item Bump Pitch Bump Width Bump height Bump space 1 Bump space 2 Bump area Chip boundary Symbol A B C D E BxC F Size 23um 21um 96um 35um 25um 2016um2 45~70um T 2. Input Pads Boundary (Include Scribe Land) .m bt T T T T T T T T w A B G C w D Item Bump Pitch Bump Pitch1 Bump Width Bump height Bump space 1 Bump space 2 Bump area Chip boundary Symbol A B C D E F BxC G w E F Size 64um 80um 55um 96um 9um 25um 5280um2 45~70um 3. Alignment Marks E B C A C C B E E D C C B E E BC C C B E A E B C C C B E DGNDO LCM 1 LCM 0 V D D IO T E S T /D U M M Y 1 T E S T /D U M M Y 2 T E S T /D U M M Y 3 T E S T /D U M M Y 4 T E S T /D U M M Y 5 D 17 D 17 D 16 D 16 D 15 D 15 D 14 D 14 D 13 D 13 D 12 D 12 D 11 D 11 D 10 D 10 D9 D9 D8 D8 DGNDO DGNDO D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D 0 (S D A ) D 0 (S D A ) T E S T /D U M M Y 6 T E S T /D U M M Y 7 T E S T /D U M M Y 8 T E S T /D U M M Y 9 E S T /D U M M Y 1 0 OSC TE CSX RDX WRX SDA E S T /D U M M Y 1 1 E S T /D U M M Y 1 2 E S T /D U M M Y 1 3 RESX DGND D /C X DGND SCL DGND PCLK DGND DE HS VS DUMMY E S T /D U M M Y 1 4 E S T /D U M M Y 1 5 E S T /D U M M Y 1 6 E S T /D U M M Y 1 7 E S T /D U M M Y 1 8 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND VD D _18V VD D _18V VD D _18V VD D _18V VD D _18V V D D IO V D D IO V D D IO V D D IO V D D IO V D D IO V D D IO V D D IO VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GVDD GVDD GVDD GVDD AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND VREF VREF VREF VREF VREF DRV DRV FB VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML V C I1 V C I1 V C I1 V C I1 V C I1 AVDD AVDD AVDD AVDD AVDD AVDD C 11P C 11P C 11P C 11P C 11N C11N C11N C11N C 12P C 12P C12P C12P C 12N C 12N C 12N C 12N AGND AGND AGND AGND AGND nd .co m G7 G3 DUM G G M Y 5 1 M Y DUM DUM S2 S4 S6 S8 S10 M Y DUMM S1 S3 S5 S7 S9 S11 Y re SPFD54126B (Top View) S264 DUM DUM S265 M M Y Y S263 DUM DUM M M Y Y Y DUMM S266 S522 S524 S526 S528 DUMM S521 S523 S525 S527 DUMM Y Y DUM G2 G6 G 10 M Y DUM G4 G8 M Y Al layer A Clearance area Polyomide Symbol A B D C AxA E Gap Size 105um 15um 40um 25um 11025um 2 40~48um Alignment mark size Clearance gap1 Clearance gap2 Alignment mark width Alignment area Gap width C C C C C C C C C C C C C C C C C C PA V V V V V V PA PA VCL VCL VCL 21P 21P 21P 21N 21N 21N 22P 22P 22P 22N 22N 22N 23P 23P 23P 23N 23N 23N VGL VGL VGL VGH VGH VGH DB0 COM COM COM COM COM COM DA2 DB2 G2 G2 G2 G2 G2 DU DU 04 08 12 16 20 MMY MMY G G G G D P P 2 2 2 2 U A A 06 10 14 18 MMY DB3 DA3 (c) ORISE Technology Co., Ltd. Proprietary & Confidential 221 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 9.2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 PAD Locations Name X Y Name X Y Name X Y PADA1 PADB1 PADA0 VOTP VOTP EXTC VDDIO IM0 IM1 IM2 P68 DGNDO SPI_CSX Dummy Dummy VDDIO RCM0 RCM1 DGNDO SRGB SMX SMY VDDIO PREG RL TB SHUT IDM REV DGNDO GM1 GM0 VDDIO DGNDO LCM1 LCM0 VDDIO TEST/Dummy TEST/Dummy TEST/Dummy TEST/Dummy TEST/Dummy DB17 DB17 DB16 DB16 DB15 DB15 DB14 DB14 DB13 DB13 DB12 DB12 125 205 285 365 445 525 605 685 765 845 925 1005 1085 1165 1245 1325 1405 1485 1565 1645 1725 1805 1885 1965 2045 2125 2205 2285 2365 2445 2525 2605 2685 3165 3245 3325 3405 3485 3565 3645 3725 3805 3885 3949 4029 4093 4173 4237 4317 4381 4461 4525 4605 4669 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 DB11 DB11 DB10 DB10 DB9 DB9 DB8 DB8 DGNDO DGNDO DB7 DB7 DB6 DB6 DB5 DB5 DB4 DB4 DB3 DB3 DB2 DB2 DB1 DB1 DB0 DB0 TEST/Dummy TEST/Dummy TEST/Dummy TEST/Dummy TEST/Dummy OSC TE CSX RDX WRX SDA TEST/Dummy TEST/Dummy TEST/Dummy RESX DGNDO DCX DGNDO SCL DGNDO PCLK DGNDO DE HS VS Dummy TEST/Dummy TEST/Dummy 4749 4813 4893 4957 5037 5101 5181 5245 5325 5389 5469 5533 5613 5677 5757 5821 5901 5965 6045 6109 6189 6253 6333 6397 6477 6541 6621 6701 6781 6861 6941 7021 7101 7181 7261 7341 7421 7501 7581 7661 7741 7821 7901 7981 8061 8141 8221 8301 8381 8461 8541 8621 8701 8781 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 TEST/Dummy TEST/Dummy TEST/Dummy DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND VCC VCC VCC VCC VCC VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GVDD GVDD GVDD GVDD AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND VREF VREF 8861 8941 9021 9101 9165 9229 9293 9357 9421 9485 9549 9613 9677 9741 9805 9885 9949 10013 10077 10141 10221 10285 10349 10413 10477 10541 10605 10669 10749 10813 10877 10941 11005 11069 11133 11197 11261 11325 11405 11469 11533 11597 11677 11741 11805 11869 11933 11997 12061 12125 12189 12253 12333 12397 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 222 re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Name X Y Name X Y Name X Y 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 VREF VREF VREF DRV DRV FB VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCI1 VCI1 VCI1 VCI1 VCI1 AVDD AVDD AVDD AVDD AVDD AVDD C11P C11P C11P C11P C11N C11N C11N C11N C12P C12P C12P C12P C12N C12N C12N C12N AGND AGND AGND AGND AGND VCL VCL VCL C21P C21P C21P C21N C21N C21N 12461 12525 12589 12669 12749 12829 12909 12973 13037 13101 13181 13245 13309 13373 13453 13517 13581 13645 13709 13789 13853 13917 13981 14045 14109 14189 14253 14317 14381 14461 14525 14589 14653 14733 14797 14861 14925 15005 15069 15133 15197 15277 15341 15405 15469 15533 16013 16077 16141 16221 16285 16349 16429 16493 16557 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 C22P C22P C22P C22N C22N C22N C23P C23P C23P C23N C23N C23N VGL VGL VGL VGH VGH VGH PADB0 VCOM VCOM VCOM VCOM VCOM VCOM 16637 16701 16765 16845 16909 16973 17053 17117 17181 17261 17325 17389 17469 17533 17597 17677 17741 17805 17885 17965 18029 18093 18157 18221 18285 18365 18445 18485 18462 18439 18416 18393 18370 18347 18324 18301 18278 18255 18232 18209 18186 18163 18140 18117 18094 18071 18048 18025 18002 17979 17956 17933 17910 17887 17864 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 273 274 275 276 277 278 279 280 281 282 283 284 285 G174 G172 G170 G168 G166 G164 G162 G160 G158 G156 G154 G152 G150 G148 G146 G144 G142 G140 G138 G136 G134 G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100 G98 G96 G94 G92 G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 17841 17818 17795 17772 17749 17726 17703 17680 17657 17634 17611 17588 17565 17542 17519 17496 17473 17450 17427 17404 17381 17358 17335 17312 17289 17266 17243 17220 17197 17174 17151 17128 17105 17082 17059 17036 17013 16990 16967 16944 16921 16898 16875 16852 16829 16806 16783 16760 16737 16714 16691 16668 16645 16622 16599 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 nd .co 223 re bt PADA2 PADB2 PADA3 Dummy7 PADB3 Dummy8 Dummy9 G220 G218 G216 G214 G212 G210 G208 G206 G204 G202 G200 G198 G196 G194 G192 G190 G188 G186 G184 G182 G180 G178 G176 .m 243 244 245 246 247 248 249 w w w 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 (c) ORISE Technology Co., Ltd. Proprietary & Confidential m 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Name X Y Name X Y Name X Y 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 G64 G62 G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 Dummy Dummy Dummy Dummy S528 S527 S526 S525 S524 S523 S522 S521 S520 S519 S518 S517 S516 S515 S514 S513 S512 S511 S510 16576 16553 16530 16507 16484 16461 16438 16415 16392 16369 16346 16323 16300 16277 16254 16231 16208 16185 16162 16139 16116 16093 16070 16047 16024 16001 15978 15955 15932 15909 15886 15863 15840 15817 15449 15426 15403 15380 15357 15334 15311 15288 15265 15242 15219 15196 15173 15150 15127 15104 15081 15058 15035 15012 14989 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 S509 S508 S507 S506 S505 S504 S503 S502 S501 S500 S499 S498 S497 S496 S495 S494 S493 S492 S491 S490 S489 S488 S487 S486 S485 S484 S483 S482 S481 S480 S479 S478 S477 S476 S475 S474 S473 S472 S471 S470 S469 S468 S467 S466 S465 S464 S463 S462 S461 S460 S459 S458 S457 S456 S455 14966 14943 14920 14897 14874 14851 14828 14805 14782 14759 14736 14713 14690 14667 14644 14621 14598 14575 14552 14529 14506 14483 14460 14437 14414 14391 14368 14345 14322 14299 14276 14253 14230 14207 14184 14161 14138 14115 14092 14069 14046 14023 14000 13977 13954 13931 13908 13885 13862 13839 13816 13793 13770 13747 13724 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 438 439 440 441 442 443 444 445 446 447 448 449 450 S454 S453 S452 S451 S450 S449 S448 S447 S446 S445 S444 S443 S442 S441 S440 S439 S438 S437 S436 S435 S434 S433 S432 S431 S430 S429 S428 S427 S426 S425 S424 S423 S422 S421 S420 S419 S418 S417 S416 S415 S414 S413 S412 S411 S410 S409 S408 S407 S406 S405 S404 S403 S402 S401 S400 13701 13678 13655 13632 13609 13586 13563 13540 13517 13494 13471 13448 13425 13402 13379 13356 13333 13310 13287 13264 13241 13218 13195 13172 13149 13126 13103 13080 13057 13034 13011 12988 12965 12942 12919 12896 12873 12850 12827 12804 12781 12758 12735 12712 12689 12666 12643 12620 12597 12574 12551 12528 12505 12482 12459 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 nd .co 224 re bt .m w w w (c) ORISE Technology Co., Ltd. Proprietary & Confidential m 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Name X Y Name X Y Name X Y 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 12436 12413 12390 12367 12344 12321 12298 12275 12252 12229 12206 12183 12160 12137 12114 12091 12068 12045 12022 11999 11976 11953 11930 11907 11884 11861 11838 11815 11792 11769 11746 11723 11700 11677 11654 11631 11608 11585 11562 11539 11516 11493 11470 11447 11424 11401 11378 11355 11332 11309 11286 11263 11240 11217 11194 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 11171 11148 11125 11102 11079 11056 11033 11010 10987 10964 10941 10918 10895 10872 10849 10826 10803 10780 10757 10734 10711 10688 10665 10642 10619 10596 10573 10550 10527 10504 10481 10458 10435 10412 10389 10366 10343 10320 10297 10274 10251 10228 10205 10182 10159 10136 10113 10090 10067 10044 10021 9998 9975 9952 9929 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 603 604 605 606 607 608 609 610 611 612 613 614 615 S289 S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 Dummy Dummy Dummy Dummy Dummy S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 9906 9883 9860 9837 9814 9791 9768 9745 9722 9699 9676 9653 9630 9607 9584 9561 9538 9515 9492 9469 9446 9423 9400 9377 9354 9331 9308 9285 9262 9239 9216 9193 9170 9147 9124 9101 9078 9055 9032 9009 8986 8963 8940 8917 8894 8871 8848 8825 8802 8779 8756 8733 8710 8687 8664 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 nd .co 225 re bt .m w w w (c) ORISE Technology Co., Ltd. Proprietary & Confidential m 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Name X Y Name X Y Name X Y 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 8641 8618 8595 8572 8549 8526 8503 8480 8457 8434 8411 8388 8365 8342 8319 8296 8273 8250 8227 8204 8181 8158 8135 8112 8089 8066 8043 8020 7997 7974 7951 7928 7905 7882 7859 7836 7813 7790 7767 7744 7721 7698 7675 7652 7629 7606 7583 7560 7537 7514 7491 7468 7445 7422 7399 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 7376 7353 7330 7307 7284 7261 7238 7215 7192 7169 7146 7123 7100 7077 7054 7031 7008 6985 6962 6939 6916 6893 6870 6847 6824 6801 6778 6755 6732 6709 6686 6663 6640 6617 6594 6571 6548 6525 6502 6479 6456 6433 6410 6387 6364 6341 6318 6295 6272 6249 6226 6203 6180 6157 6134 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 768 769 770 771 772 773 774 775 776 777 778 779 780 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 6111 6088 6065 6042 6019 5996 5973 5950 5927 5904 5881 5858 5835 5812 5789 5766 5743 5720 5697 5674 5651 5628 5605 5582 5559 5536 5513 5490 5467 5444 5421 5398 5375 5352 5329 5306 5283 5260 5237 5214 5191 5168 5145 5122 5099 5076 5053 5030 5007 4984 4961 4938 4915 4892 4869 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 nd .co 226 re bt .m w w w (c) ORISE Technology Co., Ltd. Proprietary & Confidential m 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Name X Y Name X Y Name X Y 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 4846 4823 4800 4777 4754 4731 4708 4685 4662 4639 4616 4593 4570 4547 4524 4501 4478 4455 4432 4409 4386 4363 4340 4317 4294 4271 4248 4225 4202 4179 4156 4133 4110 4087 4064 4041 4018 3995 3972 3949 3926 3903 3880 3857 3834 3811 3788 3765 3742 3719 3696 3673 3650 3627 3604 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 Dummy Dummy Dummy Dummy G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 G59 G61 G63 3581 3558 3535 3512 3489 3466 3443 3420 3397 3374 3351 3328 3305 3282 3259 3236 3213 3190 3167 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 933 934 935 936 937 938 939 940 941 942 943 944 945 G65 G67 G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 G133 G135 G137 G139 G141 G143 G145 G147 G149 G151 G153 G155 G157 G159 G161 G163 G165 G167 G169 G171 G173 1971 1948 1925 1902 1879 1856 1833 1810 1787 1764 1741 1718 1695 1672 1649 1626 1603 1580 1557 1534 1511 1488 1465 1442 1419 1396 1373 1350 1327 1304 1281 1258 1235 1212 1189 1166 1143 1120 1097 1074 1051 1028 1005 982 959 936 913 890 867 844 821 798 775 752 729 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 nd .co 3144 3121 2753 2730 2707 2684 2661 2638 2615 2592 2569 2546 2523 2500 2477 2454 2431 2408 2385 2362 2339 2316 2293 2270 2247 2224 2201 2178 2155 2132 2109 2086 2063 2040 2017 1994 646 777 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 777 646 re 227 bt .m w w 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 w (c) ORISE Technology Co., Ltd. Proprietary & Confidential m 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Name X Y Name X Y Name X Y 988 989 990 991 992 993 994 995 996 997 998 G175 G177 G179 G181 G183 G185 G187 G189 G191 G193 G195 706 683 660 637 614 591 568 545 522 499 476 646 777 646 777 646 777 646 777 646 777 646 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 G197 G199 G201 G203 G205 G207 G209 G211 G213 G215 G217 453 430 407 384 361 338 315 292 269 246 223 777 646 777 646 777 646 777 646 777 646 777 1010 1011 1012 1013 1014 1015 G219 Dummy Dummy PADA4 Dummy PADB4 200 177 154 131 108 85 646 777 646 777 646 777 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 228 bt re nd .co Apr. 25, 2006 Preliminary Version: 0.1 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 9.3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Wiring Resistance Name Resistance Priority Name Resistance Priority Name Resistance Priority PADA1 PADB1 PADA0 VOTP VOTP EXTC VDDIO IM0 IM1 IM2 P68 DGNDO SPI_CSX Dummy Dummy VDDIO RCM0 RCM1 DGNDO SRGB SMX SMY VDDIO PREG RL TB SHUT IDM REV DGNDO GM1 GM0 VDDIO DGNDO LCM1 LCM0 VDDIO TEST/Dummy TEST/Dummy TEST/Dummy TEST/Dummy TEST/Dummy DB17 DB17 DB16 DB16 DB15 DB15 DB14 DB14 DB13 DB13 DB12 DB12 open open (200 ohm) 10 ohm 200 ohm open 200 ohm 200 ohm 200 ohm 200 ohm open 100 ohm open open open 200 ohm 200 ohm open 200 ohm 200 ohm 200 ohm open open 200 ohm 200 ohm 200 ohm 200 ohm 200 ohm open 200 ohm 200 ohm open open 200 ohm 200 ohm open open open open open open 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 4 4 4 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 DB11 DB11 DB10 DB10 DB9 DB9 DB8 DB8 DGNDO DGNDO DB7 DB7 DB6 DB6 DB5 DB5 DB4 DB4 DB3 DB3 DB2 DB2 DB1 DB1 DB0 DB0 TEST/Dummy TEST/Dummy TEST/Dummy TEST/Dummy TEST/Dummy OSC TE CSX RDX WRX SDA TEST/Dummy TEST/Dummy TEST/Dummy RESX DGNDO DCX DGNDO SCL DGNDO PCLK DGNDO DE HS VS Dummy TEST/Dummy TEST/Dummy 100 ohm 100 ohm 100 ohm 100 ohm open open 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm open open open open open open 100 ohm 100 ohm 100 ohm 100 ohm 100 ohm open open open 200 ohm open 100 ohm open 100 ohm open 100 ohm open 100 ohm 100 ohm 100 ohm open open open 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 TEST/Dummy TEST/Dummy TEST/Dummy DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND VCC VCC VCC VCC VCC VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GVDD GVDD GVDD GVDD AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND VREF VREF open open open 4 4 4 10 ohm 1 nd .co m 10 ohm 2 .m bt re 10 ohm 2 w w w 10 ohm 1 10 ohm 1 20 ohm 3 10 ohm 1 10 ohm 3 (c) ORISE Technology Co., Ltd. Proprietary & Confidential 229 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Name Resistance Priority Name Resistance Priority Name Resistance Priority 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 VREF VREF VREF DRV DRV FB VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCI1 VCI1 VCI1 VCI1 VCI1 AVDD AVDD AVDD AVDD AVDD AVDD C11P C11P C11P C11P C11N C11N 10 ohm 2 10 ohm 2 20 ohm 1 10 ohm 2 30 ohm 2 30 ohm 2 (30 ohm) (30 ohm) 3 4 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 C11N C11N C12P C12P C12P C12P C12N C12N C12N C12N AGND AGND AGND AGND AGND VCL VCL VCL C21P C21P C21P C21N C21N C21N C22P C22P C22P C22N C22N C22N C23P 30 ohm 3 30 ohm 3 30 ohm 3 20 ohm 20 ohm 30 ohm 3 3 3 10 ohm 1 10 ohm 2 10 ohm 2 225 226 227 228 229 230 231 232 233 234 235 236 237 C23P C23P C23N C23N C23N VGL VGL VGL VGH VGH VGH PADB0 VCOM VCOM VCOM VCOM VCOM VCOM PADA2 PADB2 open open 4 4 10 ohm 1 (200 ohm) 4 10 ohm 2 10 ohm 10 ohm 2 2 30 ohm 3 nd .co re 30 ohm 3 bt 230 .m (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w m 238 239 240 241 242 243 244 245 246 247 248 249 250 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by ORISE Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. ORISE Technology makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. alter the specifications and prices at any time without notice. applications. FURTHERMORE, ORISE Technology MAKES NO ORISE Technology reserves the right to halt production or Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by ORISE Technology for such applications. Please note that application circuits illustrated in this document are for reference purposes only.. (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 231 bt re nd .co Apr. 25, 2006 Preliminary Version: 0.1 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 10. REVISION HISTORY Date Revision # Description 1. Change title: Package/PAD Locations to PAD Locations 2. Modify 2. FEATURE 3. Modify Table 6.1.2. (4) to (4) ~ (9) 4. Modify Description of 6.3.19. NOV. 20, 2006 0.2 5. Modify 6.3.22 Table 6. Modify 6.3.23 Table 7. Modify 6.3.23 Table 8. Modify 6.3.23 Table 10. Modify 6.3.23 Table OCT. 26, 2006 0.1 Original 9. Modify 6.3.23 Table Page 220 6 20-22 108 112.113 114.115 116.117 118.119 120.121 122.123 218 (c) ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 232 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 |
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